The choice of transistor technology (bipolar, CMOS, or JFET) has a significant effect on input bias current. Bipolar transistors are current controlled devices, whereas CMOS and JFET are voltage controlled. The bipolar transistor collector current is equal to base current multiplied by a current gain. Thus, it is required to have a minimum base current for all bipolar transistors to operate. Because CMOS devices are voltage controlled, the drain current is controlled by a voltage from gate to source. Also, the gate is insulated from the drain-to-source channel with a layer of metal-oxide so the input impedance is very high and there is effectively no leakage current. A JFET device is also a voltage-controlled device. The JFET transistor uses a reverse-biased gate to source P-N junction voltage to control the drain current. Thus, there will be a very small reverse bias leakage current. However, compared to the base current of a bipolar transistor, the JFET gate current is negligible (see Figure 2-4).

The base current of the input stage is the input bias current (I_B) in a bipolar op amp. Depending on the bandwidth, slew rate, and process technology the input bias current of uncorrected bipolar op amps can range from nano-amps to micro-amps. The two inputs also have some leakage current due to ESD structures but this current is generally negligible compared to the base current (see Figure 2-5). Also, the input transistors are not perfectly matched, so the I_B flowing into each amplifier differs slightly. This difference is referred to is bias current offset (I_OS). Conversely, the I_B of CMOS and JFET devices, is primarily due to the leakage of the ESD structures and will generally be in the pico-amp or femto-amp range at room temperature (see Figure 2-6).

I_B is generally specified in the data sheet table at room temperature and across different temperature ranges (see Table 2-1). The data sheet table generally only tells the maximum bias current over temperature. The characteristic curves provide additional detail to help understand the shape of the I_B vs temperature curve (see Figure 2-7). This relationship is quite different when comparing bipolar to CMOS/JFET devices. Because I_B in CMOS and JFET devices is mainly from the leakage of the input ESD diodes, the I_B drift over temperature is the change in leakage current over temperature. In general, the leakage of a silicon diode doubles every 10°C. Thus, at room temperature the I_B for a CMOS device is typically in the low pico-amp level, and at high temperatures the I_B can increase to nano-amp levels (see Figure 2-7).

For bipolar devices the I_B versus temperature relationship is more complex. It depends on the overall biasing temperature coefficient of the input stage and also on the relationship between current gain and temperature. Thus, the input bias current of some bipolar devices is constant over temperature (in zero-TC biasing), some devices increase over temperature in PTAT (proportionate to absolute temperature) biasing, and others decrease over temperature in CTAT (counter to absolute temperature) biasing. The temperature coefficient for these biasing schemes is mainly valid below 85°C. Above 85°C the input bias current for bipolar devices typically increase by a factor of 3× to 5× due to a decrease in the beta of the input transistors. In CMOS or JFET devices the input bias current usually increases by a factor of 1000× between room temperature and 125°C due to the ESD diode leakage doubling every 10°C (see Figure 2-7).

Figure 2-7 compares I_B over temperature for a CMOS device to the bipolar device shown in Figure 2-8. The CMOS graph vertical axis is logarithmic and I_B increases from about 200fA to 500pA across temperature (increases by 2,500×). Conversely, the bipolar amplifier bias current increases slightly at 85°C by a factor of 2× or 3×. Although the CMOS device current increases by a much higher factor than that of the bipolar device, the absolute magnitude of the I_B in bipolar is larger. In the example curve you can see the bipolar has I_B above 3nA at 125°C, whereas the CMOS device has I_B of 0.5 nA at 125°C. Thus, at high temperature the example CMOS device has lower bias current than the bipolar device. The key point here is that when performing error analysis for I_B on CMOS devices, it is very important to consider the operating temperature range of the application.