SBOS853B March   2017  – December 2024

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements #GUID-D86987F5-A9B7-4506-9858-90867D8ED8B3/SBOS6814062
    7. 5.7 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Human Eye Matching
      2. 6.3.2 Automatic Full-Scale Range Setting
      3. 6.3.3 Interrupt Operation, INT Pin, and Interrupt Reporting Mechanisms
      4. 6.3.4 I2C Bus Overview
        1. 6.3.4.1 Serial Bus Address
        2. 6.3.4.2 Serial Interface
    4. 6.4 Device Functional Modes
      1. 6.4.1 Automatic Full-Scale Setting Mode
      2. 6.4.2 Interrupt Reporting Mechanism Modes
        1. 6.4.2.1 Latched Window-Style Comparison Mode
        2. 6.4.2.2 Transparent Hysteresis-Style Comparison Mode
        3. 6.4.2.3 End-of-Conversion Mode
        4. 6.4.2.4 End-of-Conversion and Transparent Hysteresis-Style Comparison Mode
    5. 6.5 Programming
      1. 6.5.1 Writing and Reading
        1. 6.5.1.1 High-Speed I2C Mode
        2. 6.5.1.2 General-Call Reset Command
        3. 6.5.1.3 SMBus Alert Response
  8. 7 Register Maps
    1. 7.1 Internal Registers
      1. 7.1.1 Register Descriptions
        1. 7.1.1.1 Result Register (offset = 00h)
        2. 7.1.1.2 Configuration Register (offset = 01h) [reset = C810h]
        3. 7.1.1.3 Low-Limit Register (offset = 02h) [reset = C0000h]
        4. 7.1.1.4 High-Limit Register (offset = 03h) [reset = BFFFh]
        5. 7.1.1.5 Manufacturer ID Register (offset = 7Eh) [reset = 5449h]
        6. 7.1.1.6 Device ID Register (offset = 7Fh) [reset = 3001h]
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Electrical Interface
      2. 8.1.2 Optical Interface
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Optomechanical Design
        2. 8.2.2.2 Dark Window Selection and Compensation
      3. 8.2.3 Application Curves
    3. 8.3 Best Design Practices
    4. 8.4 Power Supply Recommendations
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
      2. 8.5.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Soldering and Handling Recommendations
    2. 11.2 DNP (S-PDSO-N6) Mechanical Drawings
    3. 11.3 DTS (SOT-5X3) Mechanical Drawings

7.1.1.3 Low-Limit Register (offset = 02h) [reset = C0000h]

This register sets the lower comparison limit for the interrupt reporting mechanisms: the INT pin, the flag high field (FH), and flag low field (FL), as described in the Section 6.4.2 section.

Figure 7-3 Low-Limit Register
15 14 13 12 11 10 9 8
LE3 LE2 LE1 LE0 TL11 TL10 TL9 TL8
R/W R/W R/W R/W R/W R/W R/W R/W
7 6 5 4 3 2 1 0
TL7 TL6 TL5 TL4 TL3 TL2 TL1 TL0
R/W R/W R/W R/W R/W R/W R/W R/W
LEGEND: R/W = Read/Write
Table 7-6 Low-Limit Register Field Descriptions
Bit Field Type Reset Description
15:12 LE[3:0] R/W 0h Exponent.
These bits are the exponent bits. Table 7-7 provides further details.
11:0 TL[11:0] R/W 000h Result.
These bits are the result in straight binary coding (zero to full-scale).

The format of this register is nearly identical to the format of the result register described in the Result Register. The low-limit register exponent (LE[3:0]) is similar to the result register exponent (E[3:0]). The low-limit register result (TL[11:0]) is similar to result register result (R[11:0]).

The equation to translate this register into the lux threshold is given in Equation 4, which is similar to the equation for the result register, Equation 3.

Equation 4. lux = 0.01 × (2LE[3:0]) × TL[11:0]

Table 7-7 gives the full-scale range and LSB size as the range and size applies to the low-limit register. The detailed discussion and examples given in for the Result Register apply to the low-limit register as well.

Table 7-7 Full-Scale Range and LSB Size as a Function of Exponent Level
LE3 LE2 LE1 LE0 FULL-SCALE RANGE (lux) LSB SIZE (lux per LSB)
0 0 0 0 40.95 0.01
0 0 0 1 81.90 0.02
0 0 1 0 163.80 0.04
0 0 1 1 327.60 0.08
0 1 0 0 655.20 0.16
0 1 0 1 1310.40 0.32
0 1 1 0 2620.80 0.64
0 1 1 1 5241.60 1.28
1 0 0 0 10483.20 2.56
1 0 0 1 20966.40 5.12
1 0 1 0 41932.80 10.24
1 0 1 1 83865.60 20.48


Note:

The result and limit registers are all converted into lux values internally for comparison. These registers can have different exponent fields. However, when using a manually-set full-scale range (configuration register, RN < 0Ch, with mask enable (ME) active), programming the manually-set full-scale range into the LE[3:0] and HE[3:0] fields can simplify the choice of programming the register. This simplification results in the user only having to think about the fractional result and not the exponent part of the result.