SBOS974E August   2019  – October 2024

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics VS = 12 V
    6. 5.6 Electrical Characteristics VS = 32 V
    7. 5.7 Timing Requirements
    8. 5.8 Typical Characteristics: VS = 12 V
    9. 5.9 Typical Characteristics: VS = 32 V
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Common-Mode Buffer
      2. 6.3.2 Thermal Protection and Package Power Dissipation
      3. 6.3.3 Output Voltage and Current Drive
      4. 6.3.4 Breakdown Supply Voltage
      5. 6.3.5 Surge Test Results
    4. 6.4 Device Functional Modes
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Applications
      1. 7.2.1 Broadband PLC Line Driving
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
        3. 7.2.1.3 Application Curve
    3. 7.3 Best Design Practices
      1. 7.3.1 Do
      2. 7.3.2 Do Not
    4. 7.4 Power Supply Recommendations
    5. 7.5 Layout
      1. 7.5.1 Layout Guidelines
        1. 7.5.1.1 Wafer and Die Information
      2. 7.5.2 Layout Examples
  9. 8 Device and Documentation Support
    1. 8.1 Development Support
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
    3. 8.3 Receiving Notification of Documentation Updates
    4. 8.4 Support Resources
    5. 8.5 Trademarks
    6. 8.6 Electrostatic Discharge Caution
    7. 8.7 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

4 Pin Configuration and Functions

Figure 4-1 RHF Package,
24-Pin VQFN With Exposed Thermal Pad
(Top View)
Figure 4-2 RGT Package,
16-Pin VQFN With Exposed Thermal Pad
(Top View)
Table 4-1 Pin Functions
PIN TYPE DESCRIPTION
NAME NO.
RHF (VQFN) RGT (VQFN)
BIAS-1(1) 23 15 Input Bias mode control, LSB
BIAS-2(1) 24 16 Input Bias mode control, MSB
D1_IN– 19 11 Input Amplifier D1 inverting input
D1_IN+ 1 1 Input Amplifier D1 noninverting input
D1_OUT 20 12 Output Amplifier D1 output
D2_IN– 18 10 Input Amplifier D2 inverting input
D2_IN+ 2 2 Input Amplifier D2 noninverting input
D2_OUT 17 9 Output Amplifier D2 output
DGND(2) 3 3 Input Ground reference for bias control pins
IADJ 4 4 Input Bias current adjustment pin
NC 6-16 6 — No internal connection
VCM 5 5 Output Common-mode buffer output
VS– 22 7, 14 Power Negative power-supply connection
VS+ 21 8, 13 Power Positive power-supply connection
Thermal Pad Pad Pad Power Electrically connected to die substrate and VS–. Connect to VS– on the printed circuit board (PCB) for best performance.
(1) The THS6222 defaults to the shutdown (disable) state if a signal is not present on the bias pins.
(2) The DGND pin ranges from VS– to (VS+) – 5V.
THS6222 YS Die,19-Pad Wafer Sale(Top View) Figure 4-3 YS Die,
19-Pad Wafer Sale
(Top View)
Table 4-2 Bond Pad Functions
PAD TYPE DESCRIPTION
NAME NO.
BIAS-1(1) 18 Input Bias mode parallel control, LSB
BIAS-2(1) 19 Input Bias mode parallel control, MSB
D1_IN– 11 Input Amplifier D1 inverting input
D1_IN+ 1 Input Amplifier D1 noninverting input
D1_OUT 13 Output Amplifier D1 output (must be used for D1 output)
D1_OUT (OPT) 12 Output Optional amplifier D1 output (pad can be left unconnected or connected to pad 13)
D2_IN– 10 Input Amplifier D2 inverting input
D2_IN+ 2 Input Amplifier D2 noninverting input
D2_OUT 8 Output Amplifier D2 output (must be used for D2 output)
D2_OUT (OPT) 9 Output Optional amplifier D2 output (can be left unconnected or connected to pad 8)
DGND(2) 3 Input Ground reference for bias control pins
IADJ 4 Input Bias-current adjustment pin
VCM 5 Output Common-mode buffer output
VS– 6, 16, 17 Power Negative power-supply connection
VS+ 7, 14, 15 Power Positive power-supply connection
Backside — — Connect to the lowest voltage potential on the die (generally VS–)
(1) The THS6222 defaults to the shutdown (disable) state if a signal is not present on the bias pins.
(2) The DGND pin ranges from VS– to (VS+) – 5V.