In addition to normal good analog layout and design practices, there are a few key items to check when designing with the PGA309.
- REFIN/REFOUT, pin 16: Keep capacitive loading to 200pF or less.
- VEXC, pin 1: Keep capacitive loading to 200pF or less.
- VSA, pin 3 and VSD, pin 10: Keep these within 200mV of each other. Internally, the PGA309 separates its digital and analog power supplies to minimize cross-talk between the two. Externally, tie the two together and bypass, directly at the pins, with a 0.1μF capacitor. If an RC filter is used between the two supplies, ensure that maximum drop is never more than 200mV.
- GNDA, pin 2 and GNDD, pin11: Ensure that these are both tied directly together and connected to the same ground point.
- VSJ, pin 8: This is the negative input to the Output Amplifier and as such, it is high-impedance. Route low-impedance traces, such as VOUT, and noisy traces away from VSJ. Minimize trace lengths to avoid unwanted additional capacitance on VSJ.
- VIN1, pin 4 and VIN2, pin 5: For source resistances greater than or equal to 10kΩ, add a capacitor of 1nF to 2nF between VIN1 and VIN2 to minimize noise coupling.
- VIN1, pin 4 and VIN2, pin 5: RFI filtering is always a concern for instrumentation amplifier applications. RFI signals injected into instrumentation amplifiers become rectified and appear on the output as a DC drift or offset; high-gain circuits amplify this effect. Figure 2-39 depicts input filtering for the PGA309. Depending upon the distance of the bridge sensor from the PGA309 and the sensor module shielding, R1 and R2 may be required. C1 should be equal to C2, and C3 should be ten times larger than C1 to attenuate any common-mode signals that become differential due to the mismatch in C1 and C2. All input filter components should be located directly at the PGA309 inputs to avoid and trace lengths from becoming receiving RFI antennas.