SBOU024C august   2004  – july 2023 PGA309

 

  1.   1
  2.   Read This First
    1.     About This Manual
    2.     Related Documentation from Texas Instruments
    3.     If You Need Assistance
    4.     Information About Cautions and Warnings
    5.     FCC Warning
    6.     Trademarks
  3. 1Introduction
    1. 1.1  PGA309 Functional Description
    2. 1.2  Sensor Error Adjustment Range
    3. 1.3  Gain Scaling
    4. 1.4  Offset Adjustment
    5. 1.5  Voltage Reference
    6. 1.6  Sensor Excitation and Linearization
    7. 1.7  ADC for Temperature Sensing
    8. 1.8  External EEPROM and Temperature Coefficients
    9. 1.9  Fault Monitor
    10. 1.10 Over-Scale and Under-Scale Limits
    11. 1.11 Power-Up and Normal Operation
    12. 1.12 Digital Interface
    13. 1.13 Pin Configuration
  4. 2Detailed Description
    1. 2.1  Gain Scaling
      1. 2.1.1 PGA309 Transfer Function
      2. 2.1.2 Solving For Gain Settings
    2. 2.2  Offset Scaling
    3. 2.3  Zero DAC and Gain DAC Architecture
    4. 2.4  Output Amplifier
    5. 2.5  Reference Voltage
    6. 2.6  Linearization Function
      1. 2.6.1 System Definitions
      2. 2.6.2 Key Linearization Design Equations
        1. 2.6.2.1 Lin DAC Counts Conversion
      3. 2.6.3 Key Ideal Design Equations
        1. 2.6.3.1 Linearization Design
        2.       37
    7. 2.7  Temperature Measurement
      1. 2.7.1 Temp ADC Start-Convert Control
      2. 2.7.2 External Temperature Sensing with an Excitation Series Resistor
    8. 2.8  Fault Monitor
    9. 2.9  Over-Scale and Under-Scale
      1. 2.9.1 Over-Scale and Under-Scale Calculation
      2.      44
    10. 2.10 Noise and Coarse Offset Adjust
    11. 2.11 General AC Considerations
  5. 3Operating Modes
    1. 3.1 Power-On Sequence and Normal Stand-Alone Operation
    2. 3.2 EEPROM Content and Temperature Lookup Table Calculation
      1. 3.2.1 Temperature Lookup Table Calculation
        1. 3.2.1.1 Temperature Lookup Table Calculation
        2.       52
        3.       53
    3. 3.3 Checksum Error Event
    4. 3.4 Test Pin
    5. 3.5 Power-On Initial Register States
      1. 3.5.1 PGA309 Power-Up State
  6. 4Digital Interface
    1. 4.1  Description
    2. 4.2  Two-Wire Interface
      1. 4.2.1 Device Addressing
      2. 4.2.2 Two-Wire Access to PGA309
    3. 4.3  One-Wire Interface
    4. 4.4  One-Wire Interface Timeout
    5. 4.5  One-Wire Interface Timing Considerations
    6. 4.6  Two-Wire Access to External EEPROM
    7. 4.7  One-Wire Interface Initiated Two-Wire EEPROM Transactions
    8. 4.8  PGA309 Stand-Alone Mode and Two-Wire Transactions
    9. 4.9  PGA309 Two-Wire Bus Master Operation and Bus Sharing Considerations
    10. 4.10 One-Wire Operation with PRG Connected to VOUT
    11. 4.11 Four-Wire Modules and One-Wire Interface (PRG)
  7. 5Application Background
    1. 5.1 Bridge Sensors
    2. 5.2 System Scaling Options for Bridge Sensors
      1. 5.2.1 Absolute Scale
      2. 5.2.2 Ratiometric Scale
    3. 5.3 Trimming Real World Bridge Sensors for Linearity
    4. 5.4 PGA309 Calibration Procedure
  8. 6Register Descriptions
    1. 6.1 Internal Register Overview
    2. 6.2 Internal Register Map
      1. 6.2.1 Register 0: Temp ADC Output Register (Read Only, Address Pointer = 00000)
      2. 6.2.2 Register 1: Fine Offset Adjust (Zero DAC) Register (Read/Write, Address Pointer = 00001)
      3. 6.2.3 Register 2: Fine Gain Adjust (Gain DAC) Register (Read/Write, Address Pointer = 00010)
      4. 6.2.4 Register 3: Reference Control and Linearization Register (Read/Write, Address Pointer = 00011)
      5. 6.2.5 Register 4: PGA Coarse Offset Adjust and Gain Select/Output Amplifier Gain Select Register (Read/Write, Address Pointer = 00100)
      6. 6.2.6 Register 5: PGA Configuration and Over/Under-Scale Limit Register (Read/Write, Address Pointer = 00101)
      7. 6.2.7 Register 6: Temp ADC Control Register (Read/Write, Address Pointer = 00110)
      8. 6.2.8 Register 7: Output Enable Counter Control Register (Read/Write, Address Pointer = 00111)
      9. 6.2.9 Register 8: Alarm Status Register (Read Only, Address Pointer = 01000)
  9.   A External EEPROM Example
    1.     A.1 PGA309 External EEPROM Example
      1.      A.1.1 Gain and Offset Scaling for External EEPROM
      2.      94
  10.   B Detailed Block Diagram
    1.     B.1 Detailed Block Diagram
  11.   C Glossary
  12.   Revision History

6.2.6 Register 5: PGA Configuration and Over/Under-Scale Limit Register (Read/Write, Address Pointer = 00101)

Bit #D15D14D13D12D11D10D9D8D7D6D5D4D3D2D1D0
Bit NameRFBRFBCLK_ CFG1CLK_ CFG0EXT ENINT ENEXT POLINT POLRFBOU ENHL2HL1HL0LL2LL1LL0
POR Value0000000000000000

Bit Descriptions:

RFB:(Reserved Factory Bit): Set to zero for proper operation

CLK_CFG[1:0]: Clocking scheme for Front-End PGA auto-zero and Coarse Offset DAC Chopping

EXTEN: Enable External Fault Comparator Group (INP_HI, INP_LO, INN_LO, INN_HI)

1 = Enable External Fault Comparator Group
0 = Disable External Fault Comparator Group

INTEN:Enable Internal Fault Comparator Group (A2SAT_LO, A2SAT_HI, A1SAT_LO, A1SAT_HI, A3_VCM)

1 = Enable Internal Fault Comparator Group
0 = Disable Internal Fault Comparator Group

EXTPOL: Selects VOUT output polarity when External Fault Comparator Group detects a fault, if EXTEN = 1

1 = Force VOUT high when any comparator in the External Fault Comparator Group detects a fault
0 = Force VOUT low when any comparator in the External Fault Comparator Group detects a fault

INTPOL: Selects VOUT output polarity when Internal Fault Comparator Group detects a fault, if INTEN = 1

1 = Force VOUT high when any comparator in the Internal Fault Comparator Group detects a fault
0 = Force VOUT low when any comparator in the Internal Fault Comparator Group detects a fault

OUEN:Over/Under-Scale Limit Enable.

1 = Enable Over/Under-Scale limits
0 = Disable Over/Under-Scale limits

HL[2:0]: Over-Scale Threshold Select

LL[2:0]: Under-Scale Threshold Select

Table 6-11 Clock Configuration (Front End PGA Auto-Zero and Coarse Adjust DAC Chopping)
ClK_CFG1
[13]		CLK_CFG0
[12]		PGA Front End
Auto-Zero		Coarse Adjust DAC
Chopping
007kHz typical3.5kHz typical
017kHz typicalOff (none)
107kHz typical, Random Clocking3.5kHz typical, Random Clocking
117kHz typical3.5kHz typical, Random Clocking
Table 6-12 Over-Scale Threshold Select (VREF = +5V)
HL2
[5]		HL1
[4]		HL0
[3]		Over-Scale Threshold
(V)		Over-Scale Threshold
0004.8540.9708 VREF
0014.8050.9610 VREF
0104.6980.9394 VREF
0114.5800.9160 VREF
1004.5510.9102 VREF
1013.6620.7324 VREF
1102.7640.5528 VREF
111Reserved—
Table 6-13 Under-Scale Threshold Select (VREF = +5V)
LL2
[2]		LL1
[1]		LL0
[0]		Under-Scale Threshold
(V)		Under-Scale Threshold
0000.1270.02540 VREF
0010.1470.02930 VREF
0100.1760.03516 VREF
0110.1960.03906 VREF
1000.2250.04492 VREF
1010.2540.05078 VREF
1100.2740.05468 VREF
1110.3030.06054 VREF