SBOU235A December   2019  – June 2020 OPA1637

 

  1.   OPA1637 Evaluation Module
    1.     Trademarks
    2. 1 Introduction
      1. 1.1 Related Documentation
      2. 1.2 Electrostatic Discharge Caution
    3. 2 Schematic, PCB Layout, and Bill of Materials
      1. 2.1 Schematic
      2. 2.2 PCB Layout
      3. 2.3 Bill of Materials
  2.   Revision History

2.2 PCB Layout

The OPA1637EVM is a four-layer PCB design. Figure 2 to Figure 6 show the PCB layer illustrations.

The top layer consists of all analog signal path traces, and is poured with a solid ground plane. To minimize second and other even-harmonic content, route traces as symmetrically as possible for both positive and negative feedback pathways. Place feedback components in close proximity to the output and input pins of the device. Position decoupling capacitors C7 and C12 on the top layer as close as possible to the power-supply pins.

The second internal layer is a dedicated solid GND plane. Place independent vias at the ground connection of every component to provide a low-impedance path to ground.

The third internal layer routes the power-supply connections.

The fourth layer routes the shutdown pin and VOCM pin connections.

sbou235_overlay.pngFigure 2. Top Overlay PCB Layout
sbou235_top.pngFigure 3. Top Layer PCB Layout
sbou235_gnd.pngFigure 4. Ground Layer PCB Layout
sbou227_pwr.pngFigure 5. Power Layer PCB Layout
sbou235_bottom.pngFigure 6. Bottom Layer PCB Layout