SBOU272 November 2021 INA2126 , INA2128
There are multiple methods of applying a reference voltage to the device. A straightforward approach is to apply a voltage to test point TP10 (TP18) with U1 and R5 (R25) not populated. If a buffered voltage is desired, U1 can be populated with an operational amplifier in an appropriate SOIC-8 (D) package and pinout. If the reference voltage is GND, R5 (R25) is populated with a 0-Ω resistor.
Reference voltage circuitry on the board provides numerous options for biasing the corresponding reference pins. The EVM layout allows for many configurations to bias the reference pin, such as: