SBOU317 September   2024

 

  1.   1
  2.   Description
  3.   Features
  4.   4
  5. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Specification
    4. 1.4 Device Information
  6. 2Hardware
    1. 2.1 Power Connections
      1. 2.1.1 Split-Supply Operation
      2. 2.1.2 Single-Supply Operation
    2. 2.2 Input and Output Connections
      1. 2.2.1 Bias Mode Control Pins
      2. 2.2.2 IADJ Pin Connection
      3. 2.2.3 Optional VCM Pin Connection
  7. 3Hardware Design Files
    1. 3.1 Schematic
    2. 3.2 Board Layout
    3. 3.3 Bill of Materials
  8. 4Additional Information
    1. 4.1 Trademarks
  9. 5Related Documentation

3.2 Board Layout

The board layers, in top to bottom order, are illustrated in Figure 3-2 through Figure 3-5.

THS6232RHFEVM Top LayerFigure 3-2 Top Layer
THS6232RHFEVM Power LayerFigure 3-4 Power Layer
THS6232RHFEVM Ground LayerFigure 3-3 Ground Layer
THS6232RHFEVM Bottom LayerFigure 3-5 Bottom Layer