SBVA088 August   2022 TPS746-Q1

 

  1.   Trademarks
  2. 1Overview
  3. 2Functional Safety Failure In Time (FIT) Rates
    1. 2.1 DRV Package
    2. 2.2 DRB Package
  4. 3Failure Mode Distribution (FMD)
  5. 4Pin Failure Mode Analysis (Pin FMA)
    1. 4.1 DRV Package
    2. 4.2 DRB Package

3 Failure Mode Distribution (FMD)

The failure mode distribution estimation for the TPS746-Q1 in Table 3-1 comes from the combination of common failure modes listed in standards such as IEC 61508 and ISO 26262, the ratio of sub-circuit function size and complexity, and from best engineering judgment.

The failure modes listed in this section reflect random failure events and do not include failures due to misuse or overstress.

Table 3-1 Die Failure Modes and Distribution
Die Failure Modes Failure Mode Distribution (%)
VOUT high (following VIN). 15%
VOUT not in specification (voltage or timing). 60%
VOUT low (no output). 15%
PG false trigger, fails to trigger. 5%
Short circuit any two pins. 5%