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  • TPS727 250-mA, Ultralow IQ, Fast Transient Response, RF Low-Dropout Linear Regulator

    • SBVS128F June   2009  – December 2015

      PRODUCTION DATA.  

  • CONTENTS
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  • TPS727 250-mA, Ultralow IQ, Fast Transient Response, RF Low-Dropout Linear Regulator
  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configurations and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Internal Current Limit
      2. 7.3.2 Soft Start
      3. 7.3.3 Shutdown
      4. 7.3.4 Dropout Voltage
      5. 7.3.5 Undervoltage Lock-out (UVLO)
      6. 7.3.6 Thermal Protection
    4. 7.4 Device Functional Modes
      1. 7.4.1 Operation with EN Control
  8. 8 Applications and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
        1. 8.2.1.1 Input and Output Capacitor Requirements
        2. 8.2.1.2 Transient Response
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Do's and Don'ts
  9. 9 Power-Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Board Layout Recommendations to Improve PSRR and Noise Performance
      2. 10.1.2 Power Dissipation
      3. 10.1.3 Package Mounting
    2. 10.2 Layout Example
      1. 10.2.1 DSE EVM Board Layout
      2. 10.2.2 YFF EVM Board Layout
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
      2. 11.1.2 Device Nomenclature
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information
  13. IMPORTANT NOTICE
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DATA SHEET

TPS727 250-mA, Ultralow IQ, Fast Transient Response, RF Low-Dropout Linear Regulator

1 Features

  • Very Low Dropout:
    • 65 mV Typical at 100 mA
    • 130 mV Typical at 200 mA
    • 163 mV Typical at 250 mA
  • 2% Accuracy Over Load, Line, Temperature
  • Ultralow IQ: 7.9 μA
  • Excellent Load Transient Performance:±50 mV for 200 mA Loading and Unloading Transient
  • Available in Fixed-Output Voltages From 0.9 V to 5 V Using Innovative Factory EEPROM Programming
  • High PSRR: 70 dB at 1 kHz
  • Stable with a 1.0-μF Ceramic Capacitor
  • Thermal Shutdown and Overcurrent Protection
  • Available in 4-Ball, 0.4-mm Pitch Wafer-Level Chip Scale and 1.5-mm × 1.5-mm SON Packages

2 Applications

  • Wireless Handsets, Smart Phones, PDAs
  • MP3 Players and Other Handheld Products
  • Wireless LAN, Bluetooth®, Zigbee®
  • Remote Controls
  • Portable Consumer Products

3 Description

The TPS727 family of low-dropout (LDO) linear regulators are ultralow quiescent current LDOs with excellent line and ultra-fast load transient performance and are designed for power-sensitive applications. The LDO output voltage level is preset by the use of innovative factory EEPROM programming. A precision band-gap and error amplifier provides overall 2% accuracy over load, line, and temperature extremes. The TPS727 family is available in 1.5-mm × 1.5-mm SON and wafer chip-scale (WCSP) packages that make the devices ideal for handheld applications. This family of devices is fully specified over a temperature range of TJ = –40°C to +125°C.

Device Information

PART NUMBER PACKAGE BODY SIZE (NOM)
TPS727xxDSE WSON (6) 1.50 mm × 1.50 mm
TPS727xxYFF DSBGA (4) 1.20 mm × 0.80 mm
  1. For all available packages, see the orderable addendum at the end of the datasheet.
TPS727 fp_all_bvs128.gif

4 Revision History

Changes from E Revision (September 2014) to F Revision

  • Changed DSBGA body size in Device Information table Go

Changes from D Revision (February 2014) to E Revision

  • Added TPS727105 to documentGo
  • Changed terminal to pin throughout documentGo
  • Updated Device Information table to current standardsGo
  • Changed Pin Configurations note Go
  • Changed Pin Functions table: reordered table by pin name, added I/O columnGo
  • Updated Handling Ratings table to current standardGo
  • Changed Thermal Information table: updated symbolsGo
  • Deleted new generation from first sentence of Overview sectionGo
  • Added note to Applications and Implementation sectionGo

Changes from C Revision (January, 2011) to D Revision

  • Changed format to meet latest data sheet standards; added new sections and moved existing sectionsGo
  • Deleted pinout diagrams from front page; see Pin Configurations and Functions section.Go
  • Changed Pin Configurations section and moved to Pin Configurations and Functions sectionGo
  • Changed note in Pin Configurations and Functions section.Go
  • Deleted Figure 26 and Figure 27Go

Changes from B Revision (April, 2010) to C Revision

  • Updated YFF front page pin drawing to show pin locationsGo
  • Revised Pin Configurations section Go
  • Changed graph title for Figure 6Go

Changes from A Revision (September, 2009) to B Revision

  • Updated Features listGo
  • Changed title of data sheetGo
  • Changed footnote 2 to Absolute Maximum Ratings tableGo
  • Revised numerous specifications and parameters in Electrical Characteristics tableGo
  • Revised operating parameters for Figure 4Go
  • Replaced Figure 5Go
  • Added operating parameters to Figure 6Go
  • Updated Figure 9Go

5 Pin Configurations and Functions

TPS72715, TPS72718, TPS72728, TPS72748
YFF Package
DSBGA-4
Top View
TPS727 po_yff_bvs128.gif
See note.
All Other TPS727 Devices
YFF Package
DSBGA-4
Top View
TPS727 po_yff_other_bvs128.gif
See note.
DSE Package
1,5mm × 1,5mm WSON-6
Top View
TPS727 po_dse_bvs128.gif
TPS727 dev_tape_reel_compare_bvs128.gif

NOTE

The EN pin is marked with a dot for the 1.5-V, 1.8-V, 2.8-V, and 4.8-V versions of the YFF package. The GND pin is marked with a dot for all other voltage versions of the YFF package. Refer to YFF0004 Package Outline page included at the end of this document for dimensions of the YFF package. On the package outline, the shaded box indicates the location of ball A1 and does not correlate to any marking on the topside of the physical package.

Pin Functions

PIN I/O DESCRIPTION
NAME YFF DSE
EN A1 4 I Enable pin. Driving EN over 0.9 V turns on the regulator. Driving EN below 0.4 V puts the regulator into shutdown mode, thus reducing the operating current to 120 nA, nominal.
GND B1 3 — Ground pin.
IN A2 6 I Input pin. A small capacitor is needed from this pin to ground to assure stability. See in the Application Information section for more details.
NC — 2, 5 — No connection. This pin can be tied to ground to improve thermal dissipation.
OUT B2 1 O Regulated output voltage pin. A small 1-μF ceramic capacitor is needed from this pin to ground to assure stability. See in the Application Information section for more details.

6 Specifications

6.1 Absolute Maximum Ratings

at TJ = –40°C to +125°C (unless otherwise noted); all voltages are with respect to GND(1)
MIN MAX UNIT
Input voltage range, VIN –0.3 +6.0 V
Enable voltage range, VEN –0.3 +6.0(2) V
Output voltage range, VOUT –0.3 +6.0 V
Maximum output current, IOUT Internally limited
Output short-circuit duration Indefinite
Operating junction temperature, TJ –55 +150 °C
Storage temperature, Tstg –55 +150 °C
(1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not implied.
(2) VEN absolute maximum rating is VIN or 6.0 V, whichever is less.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) ±2000 V
Charged device model (CDM), per JEDEC specification JESD22-C101, all pins(2) ±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating junction temperature range (unless otherwise noted)
MIN NOM MAX UNIT
VIN Input voltage 2 5.5 V
IOUT Output current 0 250 mA
TJ Operating junction temperature range –40 +125 °C

6.4 Thermal Information

THERMAL METRIC(1) TPS727 UNITS
DSE (WSON) YFF (DSBGA)
6 PINS 4 PINS
RθJA Junction-to-ambient thermal resistance 190.5 160 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 94.9 75 °C/W
RθJB Junction-to-board thermal resistance 149.3 76 °C/W
ψJT Junction-to-top characterization parameter 6.4 3 °C/W
ψJB Junction-to-board characterization parameter 152.8 74 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance(2) N/A N/A °C/W
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) θJCbot is not applicable because there is no thermal pad.

6.5 Electrical Characteristics

Over operating temperature range (TJ = –40°C to +125°C), VIN = VOUT(TYP) + 0.3 V or 2.0 V, whichever is greater; IOUT = 10 mA, VEN = 0.9 V, and COUT = 1.0 μF (unless otherwise noted). Typical values are at TJ = +25°C.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VIN Input voltage range 2.0 5.5 V
VO Output voltage range 0.9 5.0 V
VOUT (1) DC output accuracy TJ = +25°C –2.5 +2.5 mV
VOUT + 0.3 V ≤ VIN ≤ 5.5 V,
0 mA ≤ IOUT ≤ 200 mA		 –2.0% ±1.0% +2.0%
VOUT + 0.3 V ≤ VIN ≤ 5.5 V,
0 mA ≤ IOUT ≤ 250 mA		 ±1.0%
ΔVOUT Load transient 1 mA to 200 mA or
200 mA to 1 mA in 1 μs, COUT = 1 μF		 ±50.0 mV
1 mA to 250 mA or
250 mA to 1 mA in 1 μs, COUT = 1 μF		 ±65
ΔVO/ΔVIN Line regulation VOUT(NOM) + 0.3 V ≤ VIN ≤ 5.5 V,
IOUT = 10 mA		 8 μV/V
ΔVO/ΔIOUT Load regulation 0 mA ≤ IOUT ≤ 250 mA 20 μV/mA
VDO Dropout voltage(2) VIN = 0.98 × VOUT(NOM), IOUT = 10 mA 6.5 mV
VIN = 0.98 × VOUT(NOM), IOUT = 50 mA 32.5
VIN = 0.98 × VOUT(NOM), IOUT = 100 mA 65
VIN = 0.98 × VOUT(NOM), IOUT = 200 mA 130 200
VIN = 0.98 × VOUT(NOM), IOUT = 250 mA 162.5
ICL Output current limit VOUT = 0.9 × VOUT(NOM) 300 400 550 mA
IGND Ground pin current IOUT = 0 mA, TJ = –40°C to +125°C 7.9 12 µA
IOUT = 200 mA 110
IOUT = 250 mA 130
ISHDN Shutdown current (IGND) VEN ≤ 0.4 V, VIN = 2 V, TJ = +25°C 0.12 µA
VEN ≤ 0.4 V, 2.0 V < VIN ≤ 4.5 V,
TJ = –40°C to +85°C		 0.55 2
PSRR Power-supply rejection ratio VIN = 2.3 V,
VOUT = 1.8 V,
IOUT = 10 mA		 f = 10 Hz 85 dB
f = 100 Hz 75
f = 1 kHz 70
f = 10 kHz 55
f = 100 kHz 40
f = 1 MHz 45
VN Output noise voltage BW = 100 Hz to 100 kHz, VIN = 2.1 V,
VOUT = 1.8 V, IOUT = 10 mA		 33.5 μVRMS
tSTR Startup time(3) COUT = 1.0 μF, 0 ≤ IOUT ≤ 250 mA 100 μs
VHI Enable pin high (enabled) 0.9 VIN V
VLO Enable pin low (disabled) 0 0.4 V
IEN Enable pin current EN = 5.5 V 40 500 nA
UVLO Undervoltage lock-out VIN rising 1.85 1.90 1.95 V
TSD Thermal shutdown temperature Shutdown, temperature increasing +160 °C
Reset, temperature decreasing +140
TJ Operating junction temperature –40 +125 °C
(1) The output voltage is programmed at the factory.
(2) VDO is measured for devices with VOUT(NOM) ≥ 2.35 V so that VIN ≥ 2.3 V.
(3) Startup time: time from EN assertion to 0.98 × VOUT(NOM).

6.6 Typical Characteristics

Over operating temperature range (TJ = –40°C to +125°C), VIN = VOUT(TYP) + 0.3 V or 2.0 V, whichever is greater; IOUT = 10 mA, VEN = VIN, and COUT = 1.0 μF (unless otherwise noted). Typical values are at TJ = +25°C.
TPS727 tc_line_reg_10ma_bvs128.gif
IOUT = 10 mA
Figure 1. Line Regulation
(TPS72718)
TPS727 tc_load_reg_light_load_bvs128.gif
0 mA ≤ IOUT ≤ 10 mA
Figure 3. Load Regulation Under Light Loads
(TPS72718)
TPS727 tc_vdo_iout_bvs128.gif
Figure 5. Dropout Voltage vs Output Current (TPS72750)
TPS727 tc_vout_temp_bvs128.gif
Figure 7. Output Voltage vs Temperature
(TPS72718)
TPS727 tc_ignd_iout_bvs128.gif
0 mA ≤ IOUT ≤ 250 mA
Figure 9. Ground Pin Current vs Load
(TPS72718)
TPS727 tc_ishut_vin_bvs128.gif
Figure 11. Shutdown Current vs Input Voltage
(TPS72718)
TPS727 tc_psrr_fqcy_23v_bvs128.gif
Figure 13. PSRR vs Frequency
(VIN – VOUT = 0.5 V, TPS72718)
TPS727 tc_psrr_vin_bvs128.gif
Figure 15. PSRR vs Input Voltage
(TPS72718)
TPS727 tc_load_tr_01_bvs128.gif
VIN = 2.3 V, tR = tF = 1 µs
Figure 17. Load Transient Response: 0.1 mA to 200 mA
(TPS72718)
TPS727 tc_load_tr_03_bvs128.gif
VIN = 2.3 V, tR = tF = 1 µs
Figure 19. Load Transient Response: 10 mA to 200 mA
(TPS72718)
TPS727 tc_line_tr_200_bvs128.gif
Slew rate = 1 V/µs, IOUT = 200 µA
Figure 21. Line Transient Response
(TPS72718)
TPS727 tc_v_inrush_200_bvs128.gif
VIN = 2.1 V, VOUT = 1.8 V, IOUT = 200 mA
Figure 23. VIN Inrush Current
(TPS72718)
TPS727 tc_line_reg_200ma_bvs128.gif
IOUT = 200 mA
Figure 2. Line Regulation
(TPS72718)
TPS727 tc_load_reg_0ma_200ma_bvs128.gif
0 mA ≤ IOUT ≤ 250 mA
Figure 4. Load Regulation
(TPS72718)
TPS727 tc_vdo_vin_bvs128.gif
IOUT = 200 mA
Figure 6. Dropout Voltage vs Input Voltage
TPS727 tc_ignd_vin_bvs128.gif
IOUT = 0 mA
Figure 8. Ground Pin Current vs Input Voltage
(TPS72718)
TPS727 tc_ignd_temp_bvs128.gif
VIN = 2.1 V, IOUT = 0 mA
Figure 10. Ground Pin Current vs Temperature
(TPS72718)
TPS727 tc_ilim_vin_bvs128.gif
Figure 12. Current Limit vs Input Voltage
(TPS72718)
TPS727 tc_psrr_fqcy_21v_bvs128.gif
Figure 14. PSRR vs Frequency
(VIN – VOUT = 0.3 V, TPS72718)
TPS727 tc_nsd_fqcy_bvs128.gif
IOUT = 10 mA, CIN = COUT = 1 µF
Figure 16. Output Spectral Noise Density vs Output Voltage (TPS72718)
TPS727 tc_load_tr_02_bvs128.gif
VIN = 2.3 V, tR = tF = 1 µs
Figure 18. Load Transient Response: 1 mA to 200 mA (TPS72718)
TPS727 tc_line_tr_100_bvs128.gif
Slew rate = 1 V/µs, IOUT = 100 µA
Figure 20. Line Transient Response
(TPS72718)
TPS727 tc_v_inrush_100_bvs128.gif
VIN = 2.1 V, VOUT = 1.8 V, IOUT = 100 µA
Figure 22. VIN Inrush Current
(TPS72718)
TPS727 tc_v_ramp_up_down_bvs128.gif
IOUT = 200 mA
Figure 24. VIN Ramp Up, Ramp Down Response
(TPS72718)

 
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