SCAS871H February   2009  – January 2016 CDCM61004

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (Continued)
  6. 6 Pin Configuration and Functions
    1. 6.1 Pin Characteristics
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics
    6. 7.6  Typical Output Phase Noise CharacteristicsCorrected units for tRJIT (RMS phase jitter); changed to fs, RMS from ps, RMS
    7. 7.7  Typical Output Jitter Characteristics
    8. 7.8  Crystal Characteristics
    9. 7.9  Dissipation Ratings
    10. 7.10 Typical Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  Phase-Locked Loop (PLL)
      2. 9.3.2  Configuring the PLL
      3. 9.3.3  Crystal Input Interface
      4. 9.3.4  Phase Frequency Detector (PFD)
      5. 9.3.5  Charge Pump (CP)
      6. 9.3.6  On-Chip PLL Loop Filter
      7. 9.3.7  Prescaler Divider and Feedback Divider
      8. 9.3.8  On-Chip VCO
      9. 9.3.9  LVCMOS Input Interface
      10. 9.3.10 Output Divider
      11. 9.3.11 Output Buffer
    4. 9.4 Device Functional Modes
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Start-Up Time Estimation
      2. 10.1.2 Output Termination
      3. 10.1.3 LVPECL Termination
      4. 10.1.4 LVDS Termination
      5. 10.1.5 LVCMOS Termination
      6. 10.1.6 Interfacing Between LVPECL and HCSL
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Device Selection
          1. 10.2.2.1.1 Calculation Using LCM
        2. 10.2.2.2 Device Configuration
      3. 10.2.3 Application Curve
  11. 11Power Supply Recommendations
    1. 11.1 Power Considerations
    2. 11.2 Thermal Management
    3. 11.3 Power-Supply Filtering
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Device Support
      1. 13.1.1 Third-Party Products Disclaimer
    2. 13.2 Community Resources
    3. 13.3 Trademarks
    4. 13.4 Electrostatic Discharge Caution
    5. 13.5 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

5 Description (Continued)

The CDCM61004 is a high-performance, low-phase noise, fully-integrated voltage-controlled oscillator (VCO) clock synthesizer with four universal output buffers that can be configured to be LVPECL, LVDS, or LVCMOS compatible. Each universal output can also be converted to two LVCMOS outputs. Additionally, an LVCMOS bypass output clock is available in an output configuration which can help with crystal loading to achieve an exact desired input frequency. It has one fully-integrated, low-noise, LC-based VCO that operates in the
1.75 GHz to 2.05 GHz range.

The phase-locked loop (PLL) synchronizes the VCO with respect to the input, which can either be a low-frequency crystal. The output share an output divider sourced from the VCO core. All device settings are managed through a control pin structure, which has two pins that control the prescaler and feedback divider, three pins that control the output divider, two pins that control the output type, and one pin that controls the output enable. Any time the PLL settings (including the input frequency, prescaler divider, or feedback divider) are altered, a reset must be issued through the Reset control pin (active low for device reset). The reset initiates a PLL recalibration process to ensure PLL lock. When the device is in reset, the outputs and dividers are turned off.

The output frequency (fOUT) is proportional to the frequency of the input clock (fIN). The feedback divider, output divider, and VCO frequency set fOUT with respect to fIN. For a configuration setting for common wireline and datacom applications, see Table 2. For other applications, use Equation 1 to calculate the exact crystal oscillator frequency required for the desired output.

Equation 1. CDCM61004 q_fin_fout_cas869.gif

The output divider can be chosen from 1, 2, 3, 4, 6, or 8 through the use of control pins. Feedback divider and prescaler divider combinations can be chosen from 25 and 3, 24 and 3, 20 and 4, or 15 and 5, respectively, also through the use of control pins. CDCM61004 Block Diagram shows a high-level diagram of the CDCM61004.

The device operates in a 3.3-V supply environment and is characterized for operation from –40°C to 85°C.