SCAS871H February   2009  – January 2016 CDCM61004

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (Continued)
  6. 6 Pin Configuration and Functions
    1. 6.1 Pin Characteristics
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics
    6. 7.6  Typical Output Phase Noise CharacteristicsCorrected units for tRJIT (RMS phase jitter); changed to fs, RMS from ps, RMS
    7. 7.7  Typical Output Jitter Characteristics
    8. 7.8  Crystal Characteristics
    9. 7.9  Dissipation Ratings
    10. 7.10 Typical Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  Phase-Locked Loop (PLL)
      2. 9.3.2  Configuring the PLL
      3. 9.3.3  Crystal Input Interface
      4. 9.3.4  Phase Frequency Detector (PFD)
      5. 9.3.5  Charge Pump (CP)
      6. 9.3.6  On-Chip PLL Loop Filter
      7. 9.3.7  Prescaler Divider and Feedback Divider
      8. 9.3.8  On-Chip VCO
      9. 9.3.9  LVCMOS Input Interface
      10. 9.3.10 Output Divider
      11. 9.3.11 Output Buffer
    4. 9.4 Device Functional Modes
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Start-Up Time Estimation
      2. 10.1.2 Output Termination
      3. 10.1.3 LVPECL Termination
      4. 10.1.4 LVDS Termination
      5. 10.1.5 LVCMOS Termination
      6. 10.1.6 Interfacing Between LVPECL and HCSL
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Device Selection
          1. 10.2.2.1.1 Calculation Using LCM
        2. 10.2.2.2 Device Configuration
      3. 10.2.3 Application Curve
  11. 11Power Supply Recommendations
    1. 11.1 Power Considerations
    2. 11.2 Thermal Management
    3. 11.3 Power-Supply Filtering
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Device Support
      1. 13.1.1 Third-Party Products Disclaimer
    2. 13.2 Community Resources
    3. 13.3 Trademarks
    4. 13.4 Electrostatic Discharge Caution
    5. 13.5 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

12 Layout

12.1 Layout Guidelines

The CDCM61004 is a high-performance device; therefore careful attention must be paid to device configuration and printed circuit board layout with respect to power consumption. Observing good thermal layout practices enables the thermal pad on the backside of the VQFN-32 package to provide a good thermal path between the die contained within the package and the ambient air. This thermal pad also serves as the ground connection the device; therefore, a low inductance connection to the ground plane is essential.

12.2 Layout Example

Figure 26 shows a general recommendation of PCB layout with the CDCM61004 that ensures good system-level thermal reliability.

CDCM61004 pcb_lay_cas882.gif Figure 26. Recommended PCB Layout