SCAS871H February   2009  – January 2016 CDCM61004

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (Continued)
  6. 6 Pin Configuration and Functions
    1. 6.1 Pin Characteristics
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics
    6. 7.6  Typical Output Phase Noise CharacteristicsCorrected units for tRJIT (RMS phase jitter); changed to fs, RMS from ps, RMS
    7. 7.7  Typical Output Jitter Characteristics
    8. 7.8  Crystal Characteristics
    9. 7.9  Dissipation Ratings
    10. 7.10 Typical Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  Phase-Locked Loop (PLL)
      2. 9.3.2  Configuring the PLL
      3. 9.3.3  Crystal Input Interface
      4. 9.3.4  Phase Frequency Detector (PFD)
      5. 9.3.5  Charge Pump (CP)
      6. 9.3.6  On-Chip PLL Loop Filter
      7. 9.3.7  Prescaler Divider and Feedback Divider
      8. 9.3.8  On-Chip VCO
      9. 9.3.9  LVCMOS Input Interface
      10. 9.3.10 Output Divider
      11. 9.3.11 Output Buffer
    4. 9.4 Device Functional Modes
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Start-Up Time Estimation
      2. 10.1.2 Output Termination
      3. 10.1.3 LVPECL Termination
      4. 10.1.4 LVDS Termination
      5. 10.1.5 LVCMOS Termination
      6. 10.1.6 Interfacing Between LVPECL and HCSL
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Device Selection
          1. 10.2.2.1.1 Calculation Using LCM
        2. 10.2.2.2 Device Configuration
      3. 10.2.3 Application Curve
  11. 11Power Supply Recommendations
    1. 11.1 Power Considerations
    2. 11.2 Thermal Management
    3. 11.3 Power-Supply Filtering
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Device Support
      1. 13.1.1 Third-Party Products Disclaimer
    2. 13.2 Community Resources
    3. 13.3 Trademarks
    4. 13.4 Electrostatic Discharge Caution
    5. 13.5 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

11 Power Supply Recommendations

11.1 Power Considerations

As a result of the different possible configurations of the CDCM61004, Table 10 is intended to provide enough information on the estimated current consumption of the device. Unless otherwise noted, VCC = 3.3 V and
TA = 25°C.

Table 10. Estimated Block Power Consumption

BLOCK CONDITION CURRENT CONSUMPTION
(mA)		 IN-DEVICE POWER DISSIPATION
(mW)		 EXTERNAL RESISTOR
POWER
DISSIPATION
(mW)
Entire device, core current Output off, no termination resistors 65 214.5
Output buffer LVPECL output, active mode 28 42.4 50
LVCMOS output pair, static 4.5 14.85
LVCMOS output pair, transient, 'CL' load, 'f' MHz output frequency V × fOUT × (CL + 20 × 10–12) × 103 V2 × fOUT × (CL + 20 × 10–12) × 103
LVDS output, active mode 20 66
Divide circuitry Divide enabled, divide = 1 5 16.5
Divide enabled, divide = 2 10 33
Divide enabled, divide = 3, 4 15 49.5
Divide enabled, divide = 6, 8 20 66

From Table 10, the current consumption can be calculated for any configuration. For example, the current for the entire device with four LVPECL outputs in active mode can be calculated by adding up the following blocks: core current, 4x LVPECL output buffer current, and the divide circuitry current. The overall in-device power consumption can also be calculated by summing the in-device power dissipated in each of these blocks.

As an example scenario, let us consider the use case of a crystal input frequency of 25 MHz and device output frequency of 312.5 MHz in LVPECL mode. For this case, the typical overall power dissipation can be calculated as seen in Equation 5:

Equation 5. 3.3 V × (65 + 4 × 28 + 10) mA = 617.1 mW

Because each LVPECL output has two external resistors and the power dissipated by these resistors is 50 mW, the typical overall in-device power dissipation is as seen in Equation 6:

Equation 6. 617.1 mW – 4 × 50 mW = 417.1 mW

When the LVPECL output is active, the average voltage is approximately 1.9 V on each output as calculated from the LVPECL VOH and VOL specifications. Therefore, the power dissipated in each emitter resistor is approximately (1.9 V)2/150Ω = 25 mW.

When the LVCMOS output is active and drives a load capacitance, CL, the overall LVCMOS output current consumption is the sum of a static pre-driver current and a dynamic switching current (which is a function of the output frequency and the load capacitance).

Let us consider another use case of a crystal input frequency of 26.5625 MHz and device output frequency of 212.5 MHz in LVCMOS mode and driving a 5-pF load capacitance with a typical signal swing of 3.18 V. For this case, the typical overall power dissipation can be calculated as seen in Equation 7:

Equation 7. 3.3 V × (65 + 15 + 4 × 21.4) mA = 546.48 mW

11.2 Thermal Management

Power consumption of the CDCM61004 can be high enough to require attention to thermal management. For reliability and performance reasons, the die temperature should be limited to a maximum of 125°C. That is, as an estimate, TA (ambient temperature) plus device power consumption times θJA should not exceed 125°C.

The device package has an exposed pad that provides the primary heat removal path as well as an electrical grounding to the printed circuit board (PCB). To maximize the removal of heat from the package, a thermal land pattern including multiple vias to a ground plane must be incorporated on the PCB within the footprint of the package. The exposed pad must be soldered down to ensure adequate heat conduction out of the package. Check the mechanical data at the end of the data sheet for land and via pattern examples.

11.3 Power-Supply Filtering

PLL-based frequency synthesizers are very sensitive to noise on the power supply, which can dramatically increase the jitter of the PLL. This characteristic is especially true for analog-based PLLs. Thus, it is essential to reduce noise from the system power supply, especially when jitter/phase noise is very critical to applications. A PLL would have attenuated jitter as a result of power-supply noise at frequencies beyond the PLL bandwidth because of attenuation by the loop response.

Filter capacitors are used to eliminate the low-frequency noise from the power supply, where the bypass capacitors provide the very low impedance path for high-frequency noise and guard the power-supply system against the induced fluctuations. These bypass capacitors also provide instantaneous current surges as required by the device and should have low equivalent series resistance (ESR). To properly use these bypass capacitors, they must be placed very close to the power-supply pins and laid out with short loops to minimize inductance. TI recommends adding as many high-frequency (for example, 0.1-μF) bypass capacitors as there are supply pins in the package.

The CDCM61004 power-supply requirements can be grouped into two sets: the analog supply line and the output/input supply line. The analog supply line consists of the following power-supply pins on the CDCM61004: VCC_PLL1, VCC_PLL2, and VCC_VCO. These pins can be shorted together. The output/input supply line consists of the VCC_OUT and the VCC_IN power-supply pins on the CDCM61004. These pins can be shorted together. Inserting a ferrite bead between the analog supply line and the output/input supply line isolates the high-frequency switching noises generated by the device input and outputs, preventing them from leaking into the sensitive analog supply line. Choosing an appropriate ferrite bead with very low DC resistance is important because it is imperative to provide adequate isolation between the sensitive analog supply line and the other board supply lines, and to maintain a voltage at the analog power-supply pins of the CDCM61004 that is greater than the minimum voltage required for proper operation.

Figure 25 shows a general recommendation for decoupling the power supply.

CDCM61004 ai_power_supply_cas871.gif Figure 25. Recommended Power-Supply Decoupling