SCAS887B September   2009  – January 2016 CDCLVP2106

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics: LVCMOS Input, at VCC = 2.375 V to 3.6 V
    6. 6.6  Electrical Characteristics: Differential Input, at VCC = 2.375 V to 3.6 V
    7. 6.7  Electrical Characteristics: LVPECL Output, at VCC = 2.375 V to 2.625 V
    8. 6.8  Electrical Characteristics: LVPECL Output, at VCC = 3 V to 3.6 V
    9. 6.9  Timing Requirements, at VCC = 2.375 V to 2.625 V
    10. 6.10 Timing Requirements, at VCC = 3 V to 3.6 V
    11. 6.11 Typical Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1 Test Configurations
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
    4. 8.4 Device Functional Modes
      1. 8.4.1 LVPECL Output Termination
      2. 8.4.2 Input Termination
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 Power-Supply Filtering
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
    3. 11.3 Thermal Considerations
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Community Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

1 Features

  • Dual 1:6 Differential Buffer
  • Two Clock Inputs
  • Universal Inputs Can Accept LVPECL, LVDS, LVCMOS/LVTTL
  • 12 LVPECL Outputs
  • Maximum Clock Frequency: 2 GHz
  • Maximum Core Current Consumption: 92 mA
  • Very Low Additive Jitter: <100 fs, RMS in 10-kHz to 20-MHz Offset Range
  • 2.375-V to 3.6-V Device Power Supply
  • Maximum Propagation Delay: 550 ps
  • Maximum Within Bank Output Skew: 20 ps
  • LVPECL Reference Voltage, VAC_REF, Available for Capacitive-Coupled Inputs
  • Industrial Temperature Range: –40°C to +85°C
  • Supports 105°C PCB Temperature (Measured with a Thermal Pad)
  • Available in 6-mm × 6-mm, 40-Pin VQFN (RHA) Package
  • ESD Protection Exceeds 2000 V (HBM)

2 Applications

  • Wireless Communications
  • Telecommunications/Networking
  • Medical Imaging
  • Test and Measurement Equipment

3 Description

The CDCLVP2106 is a highly versatile, low additive jitter buffer that can generate 12 copies of LVPECL clock outputs from two LVPECL, LVDS, or LVCMOS inputs for a variety of communication applications. It has a maximum clock frequency up to 2 GHz. Each buffer block consists of one input that feeds two LVPECL outputs. The overall additive jitter performance is less than 0.1 ps, RMS from 10 kHz to 20 MHz, and overall output skew is as low as 20 ps, making the device a perfect choice for use in demanding applications.

The CDCLVP2106 clock buffer distributes two clock inputs (IN0, IN1) to 12 pairs of differential LVPECL clock outputs (OUT0, OUT11) with minimum skew for clock distribution. Each buffer block consists of one input that feeds two LVPECL clock outputs. The inputs can be LVPECL, LVDS, or LVCMOS/LVTTL.

The CDCLVP2106 is specifically designed for driving 50-Ω transmission lines. When driving the inputs in single-ended mode, the LVPECL bias voltage (VAC_REF) should be applied to the unused negative input pin. However, for high-speed performance up to 2 GHz, differential mode is strongly recommended.

The CDCLVP2106 is characterized for operation from –40°C to +85°C and is available in a 6-mm × 6-mm, VQFN-40 package.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)
CDCLVP2106 VQFN (40) 6.00 mm × 6.00 mm
  1. For all available packages, see the orderable addendum at the end of the data sheet.

Simplified Schematic

CDCLVP2106 fbd_cas887.gif