SCDA036A May   2022  – June 2024 TMUX8212 , TMUXS7614D

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1 Size Requirement
    1. 1.1 Optimized Layout and Control
  5. 2 Reliability Over Time
  6. 3 Power Consumption
  7. 4 Switching Speed and Hot Switching
  8. 5 Signal Isolation
  9. 6 Capacitance
  10. 7 On-Resistance and Flatness
  11. 8 Leakage Current
  12. 9 Integrated Protection
  13. 10Latch-up Immunity
  14. 11Galvanic Isolation
  15. 12Conclusion
  16. 13References
  17. 14Revision History

10 Latch-up Immunity

The likelihood of a latch-up event occurring increases in integrated analog multiplexers because of the smaller feature size and higher density placement of transistors. This is particularly true for devices that operate in harsh environments susceptible to overvoltage spikes, transients, and current injection. In these environments we recommend a latch-up immune multiplexer using processes such as silicon on insulator (SOI). For more information see Using Latch-Up Immune Multiplexers to Help Improve System Reliability