SCLA017A July   2019  – April 2021 SN74HC595

 

  1.   Trademarks
  2. 1Block Diagram
  3. 2Optimizing System Controller I/O Usage
  4. 3Logic and Translation Use Cases
    1. 3.1 Logic Use Cases
      1. 3.1.1 Combine Power Good Signals
      2. 3.1.2 Debounce Switches and Buttons
      3. 3.1.3 Increase Number of Controller Inputs
      4. 3.1.4 Increase Number of Controller Outputs
    2. 3.2 Voltage Translation Use Cases
      1. 3.2.1 SPI Communication
      2. 3.2.2 RMII Communication
  5. 4Recommended Logic and Translation Families for Network Switches
    1. 4.1 AXC: Advanced eXtremely Low-Voltage CMOS Translation
    2. 4.2 LVC: Low-Voltage CMOS Logic and Translation
    3. 4.3 HC: High-speed CMOS Logic
  6. 5Revision History

2 Optimizing System Controller I/O Usage

A network switch with 24 channels typically will have 48 or more low-current LEDs to display channel status such as established connections and data transfer. The issue with this is the number of GPIOs required to control all these LEDs. To avoid increased costs of using FPGAs or ASICS containing more I/Os, a common solution is to offload the LED driving and control to 8-bit shift registers. This reduces the 48 required GPIOs to just 3 while also increasing drive strength in most cases. Shift-registers, such as the SN74HC595, can be cascaded together to provide as many outputs as needed in the system.

For network switches that contain optical interfaces, the benefits of using a shift register can be applied to the Small Form-factor Pluggable (SFP) or Quad Small Form-factor Pluggable (QSFP) interface. Many QSFP ports will have 4 system management pins, two for input signals and two for output signals. These signals include: a reset signal for module, a module selection/enable signal, a module present signal, and an interrupt signal. The number of GPIOs needed to manage these ports can quickly get cumbersome for more complex network switches containing several of these optical interfaces. Figure 2-1 illustrates the shift register use case for a system with four QSFP ports.

GUID-8FADCD09-93FC-47FC-B989-5A6CD70926C8-low.gifFigure 2-1 I/O Expansion for Network Switch Optical Interface

The SN74HC595, a serial-in parallel-out shift register, is cascaded together resulting in twenty-four outputs to control sixteen status LEDs and 8 QSFP module management signals. The SN74HC165, a parallel-in serial-out shift register, takes the 8 signals coming from the QSFP module and outputs the data serially to the system controller. Having all shift registers share a common clock signal will allow for the system controller to perform all of this while only using a total of five GPIOs.