SCLA073 October   2024 TPLD1201 , TPLD1201-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Configuring Oscillators in TPLD
  6. 3Configuring Timing Macro-Cells in InterConnect Studio (ICS)
  7. 4Synchronizing Signals Example
  8. 5Summary
  9. 6References

3 Configuring Timing Macro-Cells in InterConnect Studio (ICS)

The oscillator dividers as well as the counter macro-cells can be utilized to generate a wide variety of frequencies. The frequency of a counter output can be calculated by: fout = fclk/(DATA + 1). After a reset occurs, an additional 2 clock cycles are needed for clock synchronization.

The circuit shown below in Figure 3-1, configured in InterConnect Studio (ICS), shows an example of using the 25kHz oscillator in the TPLD1201 to generate a 625Hz square wave with 50% duty cycle. To achieve this, the oscillator pre-divider is set to divide by 2, changing the base frequency to 12.5kHz. This is input to the counter macro-cell’s clock port to generate a 1.25kHz signal, which can be calculated by using the aforementioned equation: fout = 12.5kHz/10, where fclk = 12.5kHz and DATA = 9. To achieve a 50% duty cycle, the output of the counter is then fed into a D flip-flop, which further divides the input frequency by 2, resulting in a 625Hz signal.

Timing Components Configuration in InterConnect Studio (ICS) Figure 3-1 Timing Components Configuration in InterConnect Studio (ICS)

Figure 3-2 and Figure 3-3 show simulation results of the circuit within ICS and logic analyzer captures of the circuit in the TPLD1201, respectively.

ICS Simulation Output Figure 3-2 ICS Simulation Output
Logic Analyzer Capture of TPLD1201 Output Figure 3-3 Logic Analyzer Capture of TPLD1201 Output