SFFS069 April 2021 CDCE6214-Q1 , CDCE6214Q1TM
4 Pin Failure Mode Analysis (Pin FMA)
This section provides a Failure Mode Analysis (FMA) for the pins of the CDCE6214-Q1. The failure modes covered in this document include the typical pin-by-pin failure scenarios:
- Pin short-circuited to ground (see Table 4-3)
- Pin open-circuited (see Table 4-4)
- Pin short-circuited to an adjacent pin (see Table 4-5)
- Pin short-circuited to supply (see Table 4-6)
In addition to the above mentioned pin-by-pin failure scenarios, Table 4-2 describes the assumptions that were made to determine the failure modes.
Table 4-3 through Table 4-6 also indicate how these pin conditions can affect the device as per the failure effects classification in Table 4-1.
| Class | Failure Effects |
|---|---|
| A | Potential device damage that affects functionality |
| B | No device damage, but loss of functionality |
| C | No device damage, but performance degradation |
| D | No device damage, no impact to functionality or performance |
Figure 4-1 shows the CDCE6214-Q1 pin diagram. For a detailed description of the device pins please refer to the Pin Configuration and Functions section in the CDCE6214-Q1 data sheet.
Figure 4-1 Pin DiagramPin Name | Pin No. | Assumptions |
|---|---|---|
SECREF_P | 1 | Connected to output pins of device driving CDCE6214-Q1. Can be AC-coupled, or be connected to ground if CDCE6214-Q1 is driven single-ended. |
SECREF_N | 2 | Connected to output pins of device driving CDCE6214-Q1. Can be AC-coupled, or be connected to ground if CDCE6214-Q1 is driven single-ended. |
VDD_REF | 3 | Connected to power rail |
REFSEL | 4 | Pulled up to power rail via 5-kΩ resistor, pulled down to ground via 5-kΩ resistor or left floating. |
PRIREF_P | 5 | Connected to output pins of device driving CDCE6214-Q1. Can be AC-coupled, or be connected to ground if CDCE6214-Q1 is driven single-ended. |
PRIREF_N | 6 | Connected to output pins of device driving CDCE6214-Q1. Can be AC-coupled, or be connected to ground if CDCE6214-Q1 is driven single-ended. |
OUT0 | 7 | Goes to input of the device CDCE6214-Q1 is driving |
PDN | 8 | Connected to a 0.1-µF capacitor to ground |
OUT4_N | 9 | Goes to input of the device CDCE6214-Q1 is driving |
OUT4_P | 10 | Goes to input of the device CDCE6214-Q1 is driving |
GPIO4 | 11 | Pulled up to power rail via 5-kΩ resistor, pulled down to ground via 5-kΩ resistor or left floating. |
SCL/GPIO3 | 12 | Pulled-up to power rail via 5-kΩ, assuming I2C operation |
OUT3_N | 13 | Goes to input of the device CDCE6214-Q1 is driving |
OUT3_P | 14 | Goes to input of the device CDCE6214-Q1 is driving |
VDDO_34 | 15 | Connected to power rail |
VDDO_12 | 16 | Connected to power rail |
OUT2_N | 17 | Goes to input of the device CDCE6214-Q1 is driving |
OUT2_P | 18 | Goes to input of the device CDCE6214-Q1 is driving |
SDA/GPIO2 | 19 | Pulled-up to power rail via 5-kΩ, assuming I2C operation |
GPIO1 | 20 | Pulled up to power rail via 5-kΩ resistor, pulled down to ground via 5-kΩ resistor or left floating. |
OUT1_N | 21 | Goes to input of the device CDCE6214-Q1 is driving |
OUT1_P | 22 | Goes to input of the device CDCE6214-Q1 is driving |
HW_SW_CTRL | 23 | Pulled up to power rail via 5-kΩ resistor, pulled down to ground via 5-kΩ resistor or left floating. |
VDD_VCO | 24 | Connected to power rail |
DAP | 25 | Connected to ground |
Pin Name | Pin No. | Description of Potential Failure Effect(s) | Failure Effect Class |
|---|---|---|---|
SECREF_P | 1 | Invalid input clock, PLL doesn't lock, no output clocks | B |
SECREF_N | 2 | Invalid input clock, PLL doesn't lock, no output clocks | B |
VDD_REF | 3 | Power-ground short can damage the device | A |
REFSEL | 4 | Incorrect clock input may be selected, PLL doesn't lock, no output clocks | B |
PRIREF_P | 5 | Invalid input clock, PLL doesn't lock, no output clocks | B |
PRIREF_N | 6 | Invalid input clock, PLL doesn't lock, no output clocks | B |
OUT0 | 7 | Invalid output clock | B |
PDN | 8 | Device stays in powerdown mode, no output clocks | B |
OUT4_N | 9 | Invalid output clock | B |
OUT4_P | 10 | Invalid output clock | B |
GPIO4 | 11 | Unintended input or incorrect output forced | B |
SCL/GPIO3 | 12 | No I2C communication possible | B |
OUT3_N | 13 | Invalid output clock | B |
OUT3_P | 14 | Invalid output clock | B |
VDDO_34 | 15 | Power-ground short can damage the device | A |
VDDO_12 | 16 | Power-ground short can damage the device | A |
OUT2_N | 17 | Invalid output clock | B |
OUT2_P | 18 | Invalid output clock | B |
SDA/GPIO2 | 19 | No I2C communication possible | B |
GPIO1 | 20 | Unintended input or incorrect output forced | B |
OUT1_N | 21 | Invalid output clock | B |
OUT1_P | 22 | Invalid output clock | B |
HW_SW_CTRL | 23 | Unintended input, device may start up in an incorrect state, PLL doesn’t lock, no output clocks | B |
VDD_VCO | 24 | Power-ground short can damage the device | A |
DAP | 25 | No damage | D |
Pin Name | Pin No. | Description of Potential Failure Effect(s) | Failure Effect Class |
|---|---|---|---|
SECREF_P | 1 | Invalid input clock, PLL doesn't lock, no output clocks | B |
SECREF_N | 2 | Invalid input clock, PLL doesn't lock, no output clocks | B |
VDD_REF | 3 | No power to reference input and digital blocks of circuit, PLL doesn't lock, no output clocks, no I2C communication possible. Providing input signals violates absolute maximum ratings and can cause damage to device. | A |
REFSEL | 4 | Incorrect clock input may be selected, PLL doesn't lock, no output clocks | B |
PRIREF_P | 5 | Invalid input clock, PLL doesn't lock, no output clocks | B |
PRIREF_N | 6 | Invalid input clock, PLL doesn't lock, no output clocks | B |
OUT0 | 7 | Invalid output clock | B |
PDN | 8 | Pulled high via internal weak pull-up, device is functional. | D |
OUT4_N | 9 | Invalid output clock | B |
OUT4_P | 10 | Invalid output clock | B |
GPIO4 | 11 | Unintended input or incorrect output forced | B |
SCL/GPIO3 | 12 | No I2C communication possible | B |
OUT3_N | 13 | Invalid output clock | B |
OUT3_P | 14 | Invalid output clock | B |
VDDO_34 | 15 | No power to OUT0, OUT3, and OUT4 blocks of chip, no OUT0, OUT3 and OUT4 clocks present | B |
VDDO_12 | 16 | No power to OUT1 and OUT2 blocks of chip, no OUT1 and OUT2 clocks present | B |
OUT2_N | 17 | Invalid output clock | B |
OUT2_P | 18 | Invalid output clock | B |
SDA/GPIO2 | 19 | No I2C communication possible | B |
GPIO1 | 20 | Unintended input or incorrect output forced | B |
OUT1_N | 21 | Invalid output clock | B |
OUT1_P | 22 | Invalid output clock | B |
HW_SW_CTRL | 23 | Unintended input, device may start up in an incorrect state, PLL doesn’t lock, no output clocks | B |
VDD_VCO | 24 | No power to OUT1 and OUT2 channels | B |
DAP | 25 | Device not grounded, invalid power supplied to device Providing input signals violates absolute maximum ratings and can cause damage to device. | A |
Pin Name | Pin No. | Shorted to | Description of Potentitial Failure Effect(s) | Failure Effect Class |
|---|---|---|---|---|
SECREF_P | 1 | SECREF_N | Invalid input clock, PLL doesn't lock, no output clocks | B |
SECREF_N | 2 | VDD_REF | Invalid input clock, PLL doesn't lock, no output clocks | B |
VDD_REF | 3 | REFSEL | Incorrect clock input may be selected, PLL doesn't lock, no output clocks | B |
REFSEL | 4 | PRIREF_P | Incorrect clock input may be selected, PLL doesn't lock, no output clocks | B |
PRIREF_P | 5 | PRIREF_N | Invalid input clock, PLL doesn't lock, no output clocks | B |
PRIREF_N | 6 | OUT0 | Invalid input clock, PLL doesn't lock, no output clocks | B |
OUT0 | 7 | PDN | Device may incorrectly enter/exit powerdown mode, no output clocks | B |
PDN | 8 | OUT4_N | Device may incorrectly enter/exit powerdown mode, no output clocks | B |
OUT4_N | 9 | OUT4_P | Invalid output clock | B |
OUT4_P | 10 | GPIO4 | Output clock present, voltage swing may be degraded | C |
GPIO4 | 11 | SCL/GPIO3 | Possible interference with I2C communication | B |
SCL/GPIO3 | 12 | OUT3_N | Possible interference with I2C communication | B |
OUT3_N | 13 | OUT3_P | Invalid output clock | B |
OUT3_P | 14 | VDDO_34 | Invalid output clock, could damage receiver device | B |
VDDO_34 | 15 | VDDO_12 | No damage, possibly different output swing | C |
VDDO_12 | 16 | OUT2_N | Invalid output clock, could damage receiver device | B |
OUT2_N | 17 | OUT2_P | Invalid output clock | B |
OUT2_P | 18 | SDA/GPIO2 | Possible interference with I2C communication | B |
SDA/GPIO2 | 19 | GPIO1 | Possible interference with I2C communication | B |
GPIO1 | 20 | OUT1_N | Output clock present, voltage swing may be degraded | C |
OUT1_N | 21 | OUT1_P | Invalid output clock | B |
OUT1_P | 22 | HW_SW_CTRL | Unintended input, device may start up in an incorrect state, PLL doesn’t lock, no output clocks Alternatively, output clocks may be presented and OUT1 may have degraded voltage swing | B |
HW_SW_CTRL | 23 | VDD_VCO | Unintended input, device may start up in an incorrect state, PLL doesn’t lock, no output clocks | B |
VDD_VCO | 24 | SECREF_P | Invalid input clock, PLL doesn't lock, no output clocks | B |
DAP | 25 | Any pin | DAP is connect to ground, behavior will be the same as described in Table 4-3 | N/A |
Pin Name | Pin No. | Description of Potentitial Failure Effect(s) | Failure Effect Class |
|---|---|---|---|
SECREF_P | 1 | Invalid input clock, PLL doesn't lock, no output clocks | B |
SECREF_N | 2 | Invalid input clock, PLL doesn't lock, no output clocks | B |
VDD_REF | 3 | No damage, possibly different output swing | C |
REFSEL | 4 | Incorrect clock input may be selected, PLL doesn't lock, no output clocks | B |
PRIREF_P | 5 | Invalid input clock, PLL doesn't lock, no output clocks | B |
PRIREF_N | 6 | Invalid input clock, PLL doesn't lock, no output clocks | B |
OUT0 | 7 | Invalid output clock, could damage receiver device | B |
PDN | 8 | Device never enters powerdown, device is functional | D |
OUT4_N | 9 | Invalid output clock, could damage receiver device | B |
OUT4_P | 10 | Invalid output clock, could damage receiver device | B |
GPIO4 | 11 | Unintended input or incorrect output forced | B |
SCL/GPIO3 | 12 | No I2C communication possible | B |
OUT3_N | 13 | Invalid output clock, could damage receiver device | B |
OUT3_P | 14 | Invalid output clock, could damage receiver device | B |
VDDO_34 | 15 | No damage, possibly different output swing | C |
VDDO_12 | 16 | No damage, possibly different output swing | C |
OUT2_N | 17 | Invalid output clock, could damage receiver device | B |
OUT2_P | 18 | Invalid output clock, could damage receiver device | B |
SDA/GPIO2 | 19 | No I2C communication possible | B |
GPIO1 | 20 | Unintended input or incorrect output forced | B |
OUT1_N | 21 | Invalid output clock, could damage receiver device | B |
OUT1_P | 22 | Invalid output clock, could damage receiver device | B |
HW_SW_CTRL | 23 | Unintended input, device may start up in an incorrect state, PLL doesn’t lock, no output clocks | B |
VDD_VCO | 24 | No damage, possibly different output swing | C |
DAP | 25 | Power-ground short can damage the device | A |