SFFS101 March   2021 TPS628501 , TPS628502

 

  1. 1Overview
  2. 2Functional Safety Failure In Time (FIT) Rates
  3. 3Failure Mode Distribution (FMD)
  4. 4Pin Failure Mode Analysis (Pin FMA)

Pin Failure Mode Analysis (Pin FMA)

This section provides a Failure Mode Analysis (FMA) for the pins of the TPS62850x. The failure modes covered in this document include the typical pin-by-pin failure scenarios:

Table 4-2 through Table 4-5 also indicate how these pin conditions can affect the device as per the failure effects classification in Table 4-1.

Table 4-1 TI Classification of Failure Effects
ClassFailure Effects
APotential device damage that affects functionality
BNo device damage, but loss of functionality
CNo device damage, but performance degradation
DNo device damage, no impact to functionality or performance

Figure 4-1 shows the TPS62850x pin diagram. For a detailed description of the device pins please refer to the 'Pin Configuration and Functions' section in the TPS62850x datasheet.

GUID-CF9A8882-7E85-46D8-9411-B6D48E77EDB9-low.gifFigure 4-1 Pin Diagram

Following are the assumptions of use and the device configuration assumed for the pin FMA in this section:

  • The device is operating in the typical application, please refer to the 'Simplified Schematics' on the 1st page in the TPS62850x data sheet.

Table 4-2 Pin FMA for Device Pins Short-Circuited to Ground
Pin NamePin No.Description of Potential Failure Effect(s)Failure Effect Class

VIN

1

Device does not power up

B

EN

2

Intended functionality

D

MODE/SYNC

3

Intended functionality

D

COMP/FSET

4

Intended functionality

D

FB

5

Open loop operation and device performance degradation

C

PG

6

Intended functionality

D

SW

7

Potential device damage

A

GND

8

No effect

D

Table 4-3 Pin FMA for Device Pins Open-Circuited
Pin NamePin No.Description of Potential Failure Effect(s)Failure Effect Class

VIN

1

Device does not power up

B

EN

2

Undetermined device operation; device might power up or not

B

MODE/SYNC

3

Undetermined device operation

B

COMP/FSET

4

Intended functionality

D

FB

5

Device not functional; open loop operation

B

PG

6

Intended functionality

D

SW

7

Device not functional; open loop operation

B

GND

8

Potential device damage

A

Table 4-4 Pin FMA for Device Pins Short-Circuited to Adjacent Pin
Pin NamePin No.Shorted toDescription of Potential Failure Effect(s)Failure Effect Class

VIN

1

EN

Intended functionality

D

EN

2

MODE/SYNC

Intended functionality

D

MODE/SYNC

3

COMP/FSET

No device damage, but performance degradation

C

FB

5

PG

Device not functional; open loop operation

B

PG

6

SW

Potential internal device damage

A

SW

7

GND

Potential internal device damage

A

Table 4-5 Pin FMA for Device Pins Short-Circuited to VIN
Pin NamePin No.Description of Potential Failure Effect(s)Failure Effect Class

VIN

1

Intended functionality

D

EN

2

Intended functionality; device enabled

D

MODE/SYNC

3

Intended functionality; FPWM mode

D

COMP/FSET

4

Intended functionality; device operation in fix frequency

D

FB

5

Device not functional; open loop operation

B

PG

6

Potential device damage

A

SW

7

Potential device damge

A

GND

8

Device not functional

B