SFFS144 September 2021 TCA39306-Q1

4 Pin Failure Mode Analysis (Pin FMA)

This section provides a Failure Mode Analysis (FMA) for the pins of the TCA39306-Q1. The failure modes covered in this document include the typical pin-by-pin failure scenarios:

Pin short-circuited to Ground (see Table 4-2)
Pin open-circuited (see Table 4-3)
Pin short-circuited to an adjacent pin (see Table 4-4)
Pin short-circuited to supply (see Table 4-5 and Table 4-6)

Table 4-2 through Table 4-6 also indicate how these pin conditions can affect the device as per the failure effects classification in Table 4-1.

Table 4-1 TI Classification of Failure Effects

Class	Failure Effects
A	Potential device damage that affects functionality
B	No device damage, but loss of functionality
C	No device damage, but performance degradation
D	No device damage, no impact to functionality or performance

Figure 4-1 shows the TCA39306-Q1 pin diagram. For a detailed description of the device pins, please refer to the Pin Configuration and Functions section in the TCA39306-Q1 data sheet.

Figure 4-1 Pin Diagram

Following are the assumptions of use and the device configuration assumed for the pin FMA in this section:

V_REF1 = 0 V to 5.5 V
V_REF2 = 0 V to 5.5 V

Table 4-2 Pin FMA for Device Pins Short-Circuited to Ground

Pin Name	Pin No.	Description of Potential Failure Effect(s)	Failure Effect Class
GND	1	Normal operation, no effect.	D
VREF1	2	Communication will be corrupted and possibly cut off. Potential high current draw, and device damage if current is outside of absolute maximum ratings.	A
SCL1	3	Clock line stuck low, loss of communication.	B
SDA1	4	Data line stuck low, loss of communication.	B
SDA2	5	Data line stuck low, loss of communication.	B
SCL2	6	Clock line stuck low, loss of communication.	B
VREF2	7	No effect, normal operation if switch path signal voltages are positive. Possible damage to device if switch path signal voltages are negative. Observe that the absolute maximum ratings for all pins of the device are met, otherwise device damage may be plausible.	A
EN	8	Loss of communcation, unable to turn device on.	A

Table 4-3 Pin FMA for Device Pins Open-Circuited

Pin Name	Pin No.	Description of Potential Failure Effect(s)	Failure Effect Class
GND	1	Potential for data corruption. Loss of level translation functionality.	B
VREF1	2	Potential for data corruption. Loss of level translation functionality.	B
SCL1	3	Loss of communication	B
SDA1	4	Loss of communication.	B
SDA2	5	Loss of communication.	B
SCL2	6	Loss of communication.	B
VREF2	7	Potential for data corruption. Loss of level translation functionality.	B
EN	8	Potential for data corruption. Loss of level translation functionality.	B

Table 4-4 Pin FMA for Device Pins Short-Circuited to Adjacent Pin

Pin Name	Pin No.	Shorted to	Description of Potential Failure Effect(s)	Failure Effect Class
GND	1	VREF1	Communication will be corrupted and possibly cut off. Potential high current draw, and device damage if current is outside of absolute maximum ratings.	A
VREF1	2	SCL1	Clock line stuck high, loss of communication.	B
SCL1	3	SDA1	Communication will be corrupted, clock and data shorted together.	B
SDA1	4	SDA2	Not considered. This is a corner pin.	D
SDA2	5	SCL2	Communication will be corrupted, clock and data shorted together.	B
SCL2	6	VREF2	Clock line stuck high, loss of communication.	B
VREF2	7	EN	Normal operation if operated as a level translation device. Unable to disable device if operated as a switch.	B
EN	8	GND	Not considered. This is a corner pin.	D

Table 4-5 Pin FMA for Device Pins Short-Circuited to supply (V_REF1)

Pin Name	Pin No.	Description of Potential Failure Effect(s)	Failure Effect Class
GND	1	Communication will be corrupted and possibly cut off. Potential high current draw, and device damage if current is outside of absolute maximum ratings.	A
VREF1	2	Normal operation, no effect.	D
SCL1	3	Clock line stuck high, loss of communication.	B
SDA1	4	Clock line stuck high, loss of communication.	B
SDA2	5	Clock line stuck high, loss of communication.	B
SCL2	6	Clock line stuck high, loss of communication.	B
VREF2	7	Potential for data corruption. Loss of level translation functionality.	B
EN	8	Potential for data corruption. Loss of level translation functionality.	B

Table 4-6 Pin FMA for Device Pins Short-Circuited to supply (V_REF2)

Pin Name	Pin No.	Description of Potential Failure Effect(s)	Failure Effect Class
GND	1	Communication will be corrupted and possibly cut off. Potential high current draw, and device damage if current is outside of absolute maximum ratings.	A
VREF1	2	Loss of level translation functionality.	B
SCL1	3	Clock line stuck high, loss of communication.	B
SDA1	4	Clock line stuck high, loss of communication.	B
SDA2	5	Clock line stuck high, loss of communication.	B
SCL2	6	Clock line stuck high, loss of communication.	B
VREF2	7	Normal operation, no effect.	D
EN	8	Normal operation if operated as a level translation device. Unable to disable device if operated as a switch.	B