SFFS318A October   2021  – April 2022 TLC2272A-Q1

 

  1.   Trademarks
  2. 1Overview
  3. 2Functional Safety Failure In Time (FIT) Rates
    1. 2.1 SOIC (D) 8 Package
    2. 2.2 TSSOP (PW) 8 Package
  4. 3Failure Mode Distribution (FMD)
  5. 4Pin Failure Mode Analysis (Pin FMA)
    1. 4.1 SOIC (D) 8 Package
    2. 4.2 TSSOP (PW) 8 Package
  6. 5Revision History

3 Failure Mode Distribution (FMD)

The failure mode distribution estimation for TLC2272A-Q1 in Table 3-1 comes from the combination of common failure modes listed in standards such as IEC 61508 and ISO 26262, the ratio of sub-circuit function size and complexity and from best engineering judgment.

The failure modes listed in this section reflect random failure events and do not include failures due to misuse or overstress.

Table 3-1 Die Failure Modes and Distribution
Die Failure ModesFailure Mode Distribution (%)
Output open (Hi-Z)20%
Output saturated high25%
Output saturated low25%
Output functional, out of specification voltage or timing30%