SFFS668 June 2024 LMR36503E-Q1

4 Pin Failure Mode Analysis (Pin FMA)

This section provides a failure mode analysis (FMA) for the pins of the LMR36503E-Q1. The failure modes covered in this document include the typical pin-by-pin failure scenarios:

Pin short-circuited to ground (see Table 4-2)
Pin open-circuited (see Table 4-3)
Pin short-circuited to an adjacent pin (see Table 4-4)
Pin short-circuited to supply (see Table 4-5)

Table 4-2 through Table 4-5 also indicate how these pin conditions can affect the device as per the failure effects classification in Table 4-1.

Table 4-1 TI Classification of Failure Effects

Class	Failure Effects
A	Potential device damage that affects functionality
B	No device damage, but loss of functionality
C	No device damage, but performance degradation
D	No device damage, no impact to functionality or performance

Figure 4-1 shows the LMR36503E-Q1 pin diagram. For a detailed description of the device pins please refer to the Pin Configuration and Functions section in the LMR36503E-Q1 data sheet.

1. See the data sheet for more details. Pin 1 trimmed and factory-set for externally adjustable switching frequency RT variants only.

2. Pin 1 factory-set for fixed switching frequency MODE/SYNC variants only.

3. Pin 8 trimmed and factory-set for fixed output voltage VOUT/BIAS variants only.

4. Pin 8 factory-set for adjustable output voltage FB variants only.

Figure 4-1 Pin Diagram

Table 4-2 Pin FMA for Device Pins Short-Circuited to Ground

Pin Name	Pin No.	Description of Potential Failure Effects	Failure Effect Class
RT or MODE	1	Switching frequency is 2.2MHz	D
PGOOD	2	When not in use, can be left grounded (PGOOD is not a valid signal, VOUT normal)	D
EN/UVLO	3	VOUT = 0V (Enable is off, functionality is halted)	D
VIN	4	VOUT = 0V	B
SW	5	Damage HSFET	A
BOOT	6	VOUT = 0V, HS does not turn on	B
VCC	7	VOUT = 0V	B
VOUT/BIAS or FB	8	VOUT = 0V	B
GND	9	VOUT normal	B

Table 4-3 Pin FMA for Device Pins Open-Circuited

Pin Name	Pin No.	Description of Potential Failure Effects	Failure Effect Class
RT or MODE	1	For an RT part, frequency is not defined For a MODE/SYNC part, part can go back and forth between FPWM and PFM Part is up, part is functional	D
PGOOD	2	When not in use, can be left open ( PGOOD is not a valid signal, VOUT normal)	D
EN/UVLO	3	Pin cannot be left floating	B
VIN	4	VOUT = 0V	B
SW	5	VOUT = 0V	B
BOOT	6	VOUT = 0V, HS does not turn on	B
VCC	7	VCC output is unstable, can increase above 5.5V	A
VOUT/BIAS or FB	8	VOUT = 0V. Do not float this pin	C
GND	9	VOUT can be abnormal, as reference voltage is not fixed	C

Table 4-4 Pin FMA for Device Pins Short-Circuited to Adjacent Pin

Pin Name	Pin No.	Shorted to	Description of Potential Failure Effects	Failure Effect Class
RT or MODE	1	PGOOD	If PGOOD is high and < 5.5V, Fsw = 1MHz If PGOOD is low, Fsw = 2.2MHz PGOOD absolute maximum is 20V, RT ESD damage can occur when PG goes to 20V	A
PGOOD	2	EN/UVLO	If EN/UVLO > 20V, devices connected to PGOOD pin can be damaged	A
EN/UVLO	3	VIN	VOUT normal (Enable is on, all other blocks work)	D
VIN	4	SW	Damage LSFET	A
SW	5	BOOT	VOUT = 0V, HS does not turn on, no Cboot	B
BOOT	6	VCC	Damage occurs, break VCC Pin	A
VCC	7	VOUT/BIAS or FB	Does not work, but no damage occurs	B
VOUT/BIAS or FB	8	GND	VOUT = 0V	B
GND	9	RT or MODE	VOUT normal if RT/MODE/SYNC pin is low, otherwise not functional	B

Table 4-5 Pin FMA for Device Pins Short-Circuited to Supply

Pin Name	Pin No.	Description of Potential Failure Effects	Failure Effect Class
RT or MODE	1	If Vin > 5.5V, damage occurs. If Vin < 5.5V, switching frequency is 1MHz	A
PGOOD	2	If VIN > 20V, damage to PGOOD occurs	A
EN/UVLO	3	VOUT normal (Enable is on, all other blocks work)	D
VIN	4	VOUT normal	D
SW	5	Damage LSFET	A
BOOT	6	Damage occurs, BOOT ESD clamp is damaged	A
VCC	7	If Vin > 5.5V, damage occurs	A
VOUT/BIAS or FB	8	If VIN > 20V, damage occurs	A
GND	9	VOUT = 0V	B