Once enabled,
prefetch logic keeps fetching the next 128-bit row (4 x
32-bit words) from flash bank. On detecting the
discontinuity, the prefetch buffer will be cleared. A
software test can be performed to ascertain the proper
behavior of this logic. The following sequence of operation
can be performed.
- Disable
the prefetch mechanism, enable the timer and
Watchdog. Execute a particular function which
might have linear code and code with multiple
discontinuities. Store the time “time_1” (timer
value) taken for executing this function.
- Enable
the prefetch mechanism and execute the same
function again. Store the time “time_2” (timer
value) taken for executing this function. This
value should be less than the time_1 (time_1 >
time_2). We can mark this timer value as a golden
value and should expect the same timer values for
each run of the same function.
- Since
each flash bank row has 4 x 32-bit words, number
of rows fetched from the flash bank varies as per
the code alignment within the flash bank. Hence,
user needs to make sure that the prefetch logic
test function should be aligned/located in
particular location within flash to guarantee the
same timing behavior and does not vary compile to
compile.
Similar timer-based profiling can be performed to
ascertain proper functioning of the data cache and
wait states.