SLAA249B April   2005  – September 2018 MSP430F169 , MSP430F169 , MSP430F5252 , MSP430F5252 , MSP430F5253 , MSP430F5253 , MSP430F5254 , MSP430F5254 , MSP430F5255 , MSP430F5255 , MSP430F5256 , MSP430F5256 , MSP430F5257 , MSP430F5257 , MSP430F5258 , MSP430F5258 , MSP430F5259 , MSP430F5259

 

  1.   Implementing SMBus Using MSP430™ Hardware I2C
    1.     Trademarks
    2. 1 Introduction
    3. 2 SMBus Protocols
    4. 3 Software
    5. 4 Example Code
      1. 4.1 Example 1
        1.       fet140_SMB_mstr.c(.s43)
        2.       fet140_SMB_slav.c(.s43)
      2. 4.2 Example 2
        1.       fet140_SMB_mstr_slvrst.c(.s43)
        2.       fet140_SMB_slav_slvrst.c(.s43)
      3. 4.3 Example 3
        1.       fet140_SMB_mstr_PEC.c
        2.       fet140_SMB_slave_PEC.c
      4. 4.4 Example 4
        1.       fet140_SMB_tmp175.c
    6. 5 SMBus Using the USCI I2C Peripheral
      1. 5.1 Example 1a: Timeout Implementation for Master/Slave on a MSP430F2xx Device
        1.       msp430x26x_SMB_MST_timeout.c
        2.       msp430x26x_SMB_SLV_timeout.c
      2. 5.2 Example 1b: Timeout Implementation for Master/Slave on a MSP430F5xx Device
        1.       msp430x5xx_SMB_MST_timeout.c
        2.       msp430x5xx_SMB_SLV_timeout.c
      3. 5.3 Example 2: Implementation of CRC-8 PEC
        1.       msp430x26x_SMB_mstr_PEC.c
        2.       msp430x26x_SMB_slave_PEC.c
      4. 5.4 Example 3: Implementation With SMBUS Slave TMP175
        1.       msp430x26x_SMB_tmp175.c
    7. 6 Conclusion
    8. 7 References
  2.   Revision History

1 Introduction

SMBus is a two-wire serial interface based on the principles of I2C. The two lines are serial clock (SCL) and serial data (SDA), which are tied to VCC using pullup resistors. The devices communicating on this bus can drive the lines low or release them to high impedance. This connection is a wired-AND configuration. Multiple I2C or SMBus devices can be connected on the bus, but pins of the MSP430 MCU should not be pulled above VCC. For example, if the VCC of the MSP430 MCU is at 3 V, then all devices on the bus must be pulled up to only 3 V.

A device performing data transfers on the bus can be considered as a master or a slave. Each master and slave device can either be a transmitter (send data) or a receiver (receive data), and the communication on the bus is always initiated by the master by providing a valid start condition and the SCL signal.

Multiple master and slave devices may be connected on the bus, but only one device may master the bus during a data transfer. Since more than one master may simultaneously attempt to take control of the bus and start a transmission, the I2C/SMBus protocol provides an arbitration mechanism that relies on the wired-AND connection of all devices to the bus. A master device that generates a logic high on the SDA bus loses arbitration to a master that generates a logic low on the data bus. The MSP430 MCU master transmitter that loses arbitration switches to slave receiver mode and sets the arbitration lost flag, ALIFG. [1] Each device on the bus has a unique 7-bit address, which allows a total of 128 devices to be connected on the bus. Some addresses are dedicated SMBus addresses that are reserved and must not be assigned to any SMBus device; for example, the SMBus Alert response address (0001 100b). [2]