SLAA396A June   2008  – September 2018 MSP430F5131 , MSP430F5132 , MSP430F5151 , MSP430F5152 , MSP430F5171 , MSP430F5172 , MSP430F5232 , MSP430F5234 , MSP430F5237 , MSP430F5239 , MSP430F5242 , MSP430F5244 , MSP430F5247 , MSP430F5249 , MSP430F5252 , MSP430F5253 , MSP430F5254 , MSP430F5255 , MSP430F5256 , MSP430F5257 , MSP430F5258 , MSP430F5259 , MSP430F5304 , MSP430F5308 , MSP430F5309 , MSP430F5310 , MSP430F5324 , MSP430F5325 , MSP430F5326 , MSP430F5327 , MSP430F5328 , MSP430F5329 , MSP430F5333 , MSP430F5336 , MSP430F5338 , MSP430F5340 , MSP430F5341 , MSP430F5342 , MSP430F5418 , MSP430F5418A , MSP430F5419 , MSP430F5419A , MSP430F5435 , MSP430F5435A , MSP430F5436 , MSP430F5436A , MSP430F5437 , MSP430F5437A , MSP430F5438 , MSP430F5438A , MSP430F5500 , MSP430F5501 , MSP430F5502 , MSP430F5503 , MSP430F5504 , MSP430F5505 , MSP430F5506 , MSP430F5507 , MSP430F5508 , MSP430F5509 , MSP430F5510 , MSP430F5630 , MSP430F5631 , MSP430F5632 , MSP430F5633 , MSP430F5634 , MSP430F5635 , MSP430F5636 , MSP430F5637 , MSP430F5638

 

  1.   MSP430F5xx Overview and Comparison to MSP430F2xx and MSP430F4xx
    1.     Trademarks
    2. 1 Introduction
    3. 2 Memory Mapping
    4. 3 Core Modules
      1. 3.1 Central Processing Unit (CPUX)
      2. 3.2 Power Management Module (PMM)
      3. 3.3 Unified Clock System (UCS)
      4. 3.4 System Module (SYS)
      5. 3.5 JTAG Enhanced Emulation Module (JTAG/EEM)
    5. 4 Peripheral Modules
      1. 4.1 Timer_A
      2. 4.2 Timer_B
      3. 4.3 RTC_A
      4. 4.4 DMA
      5. 4.5 MPY32
      6. 4.6 Universal Serial Communication Interface (USCI)
      7. 4.7 Digital I/O
      8. 4.8 Cyclic Redundancy Check (CRC-CCITT)
      9. 4.9 ADC12_A
  2.   Revision History

3.3 Unified Clock System (UCS)

The UCS is most similar to the MSP430F4xx FLL+ Clock module. Like the MSP430F4xx module, the UCS is based on a frequency locked loop (FLL). Although the FLL can be run open loop like its predecessor, it is normally run closed loop. The MSP430F5xx introduces a new low-frequency on-board oscillator called REFO. REFO is a trimmed 32-kHz source and can be used as a reference source into the FLL. This gives the user a very flexible, crystal-less system.

The UCS contains several clock sources that can be used as inputs into the clock system. This includes XT1, similar to LFXT1 in the MSP430F4xx, which can accept external watch crystals (32768 Hz) in low-frequency mode or 4-MHz to 32-MHz crystals in high-frequency mode. In addition, XT1 can accept a digital input source in bypass mode. Many devices contain an optional XT2 that is identical in function and performance to XT1 in high-frequency mode. Inherited from the MSP430F2xx family, the MSP430F5xx UCS contains the VLO, which is a very low-power oscillator (12 kHz typical) that can be used as a crystal-less alternative for less time-critical applications.

As in all MSP430F2xx and MSP430F4xx devices, there are three system clocks available – ACLK, MCLK, and SMCLK. For the MSP430F5xx, there is no differentiation between these three system clocks in that any of the clock sources available can be used as a source to any or all of the three system clocks. For example, ACLK can be sourced by XT1, XT2, or the DCO. Therefore, the clock system is very orthogonal with respect to clock sources and their distribution into the clock system. ACLK, MCLK, and SMCLK behave the same as in the MSP430F2xx and MSP430F4xx with respect to their enabling/disabling across the low-power modes.

Fault logic is available for XT1 and XT2 as in the MSP430F2xx and MSP430F4xx. One major difference is the handling of a low-frequency crystal fault. For the MSP430F5xx, any 32-kHz crystal fault causes the respective system clock that is sourced by the crystal to switch automatically to the REFO clock source. This allows for the system to continue to behave as close as possible prior to the fault condition. Fault flags detected in the UCS are not automatically cleared as in previous MSP430F2xx and MSP430F4xx devices and must be cleared by the user, even if the fault condition ceases to exist.

It is important to note that on all MSP430F5xx devices, the crystal input and outputs of XT1 and XT2 (when available) are shared with general-purpose I/O ports. The default reset condition on these pins is general-purpose input ports. This differs from the MSP430F4xx, which does not share the crystal pins, and the MSP430F2xx, which defaults to crystal operation when shared.