SLAA517F May 2012 – August 2021 MSP430F6720A , MSP430F6720A , MSP430F6721A , MSP430F6721A , MSP430F6723A , MSP430F6723A , MSP430F6724A , MSP430F6724A , MSP430F6725A , MSP430F6725A , MSP430F6726A , MSP430F6726A , MSP430F6730A , MSP430F6730A , MSP430F6731A , MSP430F6731A , MSP430F6733A , MSP430F6733A , MSP430F6734A , MSP430F6734A , MSP430F6735A , MSP430F6735A , MSP430F6736 , MSP430F6736 , MSP430F6736A , MSP430F6736A
The analog front end that consists of the ΣΔ ADC is differential and requires that the input voltages at the pins do not exceed ±920 mV (gain = 1). To meet this specification, the current and voltage inputs need to be divided down. In addition, the SD24 allows a maximum negative voltage of -1 V, therefore, ac signals from mains can be directly interfaced without the need for level shifters. Section 3.2.1 and Section 3.2.2 describe the analog front end used for voltage and current channels, respectively.