SLAA558A November   2012  – October 2018 MSP430F5212 , MSP430F5214 , MSP430F5217 , MSP430F5219 , MSP430F5222 , MSP430F5224 , MSP430F5229 , MSP430F5252 , MSP430F5253 , MSP430F5254 , MSP430F5255 , MSP430F5256 , MSP430F5257 , MSP430F5258 , MSP430F5259

 

  1.   Designing With MSP430F522x and MSP430F521x Devices
    1.     Trademarks
    2. 1 Split-Supply I/O Systems
    3. 2 DVIO Supplied I/Os
    4. 3 Secondary Digital Functions on DVIO Supplied I/Os
    5. 4 Split-Supply Power-Up or Power-Down Sequence
    6. 5 Reset and NMI Pin Functionality
    7. 6 XT1 and XT2 Oscillators in Bypass Mode
    8. 7 Bootloader (BSL)
      1. 7.1 BSL Entry Sequence for DVIO Supplied BSL Interface
      2. 7.2 BSL Exit Sequence for DVIO Supplied BSL Interface
    9. 8 Debugger Connections
      1. 8.1 JTAG Standard Interface
      2. 8.2 Spy-Bi-Wire Interface
      3. 8.3 Debugging Without DVIO
    10. 9 References
  2.   Revision History

2 DVIO Supplied I/Os

A group of general-purpose I/Os reside on the DVIO supply domain and are called DVIO supplied I/Os. On the MSP430F522x devices, the following I/Os reside on the DVIO supply domain: Port1 (P1.4 to P1.7), Port2, Port3, Port4, and Port7. The remaining port I/Os reside on the DVCC supply domain.

In the data sheet, these I/O ports are highlighted in the functional block diagrams and are also pointed out in the signal descriptions table for respective I/O pins. Also, the electrical characteristics of I/Os in the DVIO and the DVCC domains are specified separately in MSP430F522x, MSP430F521x Mixed-Signal Microcontrollers.