SLAA828B March   2018  – August 2021 MSP430FR2000 , MSP430FR2032 , MSP430FR2033 , MSP430FR2100 , MSP430FR2110 , MSP430FR2111 , MSP430FR2310 , MSP430FR2311 , MSP430FR2422 , MSP430FR2433 , MSP430FR2512 , MSP430FR2522 , MSP430FR2532 , MSP430FR2533 , MSP430FR2632 , MSP430FR2633 , MSP430FR4131 , MSP430FR4132 , MSP430FR4133

 

  1.   Trademarks
  2. 1Introduction
  3. 2ADC Low-Power Sampling Software Design
    1. 2.1 System Clock Source Selection
    2. 2.2 ADC Clock Source Selection
    3. 2.3 Initialization of Unused GPIO Pins
  4. 3ADC Error Correction and Experimental Testing
    1. 3.1 Error Correction
    2. 3.2 Accuracy Test
  5. 4Time-Division Multiplexing of the ADC to Achieve Additional Channel Acquisition
  6. 5Summary
  7. 6References
  8. 7Revision History

2.2 ADC Clock Source Selection

The options for the 10-bit ADC clock source in MSP430 FRAM MCUs are MODCLK, ACLK, and SMCLK. In LPM3, MODCLK and SMCLK are disabled by default. An ADC conversion start signal can enable them and then automatically disable them again when the ADC conversion is complete. To highlight the differences between the power consumption with different clock sources, the sample rate is 100 Hz.

Table 2-2 Power Consumption Data of Different Clock Sources With XT1CLK in LPM3
ADC Clock Source (1)MODCLK (5 MHz)ACLK (32 kHz)SMCLK (5 MHz)
Sampling frequency (Hz)100100100
Power consumption (mA)0.1310.1840.026
(1) Experimental conditions:
  1. Device uses a free running MCLK at 1 MHz
  2. Test hardware is the MSP430FR4133 LaunchPad development kit
  3. XT1CLK as the clock source
  4. ADC sample hold time is 8 ADCCLK cycles
  5. Unused pins are pulled down