SLAAE71 December   2022 MSPM0G1105 , MSPM0G1106 , MSPM0G1107 , MSPM0G1505 , MSPM0G1506 , MSPM0G1507 , MSPM0G3105 , MSPM0G3106 , MSPM0G3107 , MSPM0G3505 , MSPM0G3506 , MSPM0G3507

 

  1.   Abstract
  2.   Trademarks
  3. 1Overview
  4. 2Low-Power Features in PMCU
    1. 2.1 Overview
      1. 2.1.1 Power Domains and Power Modes
      2. 2.1.2 Power Management (PMU)
        1. 2.1.2.1 Supply Supervisors
        2. 2.1.2.2 Peripheral Power Control
        3. 2.1.2.3 VBOOST for Analog Muxes
      3. 2.1.3 Clock Module (CKM)
        1. 2.1.3.1 Oscillators
        2. 2.1.3.2 Clocks
      4. 2.1.4 System Controller (SYSCTL)
        1. 2.1.4.1 Asynchronous Fast Clock Requests
        2. 2.1.4.2 Shutdown Mode Handling
  5. 3Low-Power Optimization
    1. 3.1 Low-Power Basics
    2. 3.2 MSPM0 Low-Power Feature Use
      1. 3.2.1 Low-Power Modes
      2. 3.2.2 System Clock and Peripheral Operation Frequency
      3. 3.2.3 I/O Configuration
      4. 3.2.4 Event Manager
      5. 3.2.5 Analog Peripheral Low-Power Features
      6. 3.2.6 Run Code From RAM
    3. 3.3 Software Coding Strategies
    4. 3.4 Hardware Design Strategies
  6. 4Power Consumption Measurement and Evaluation
    1. 4.1 Current Evaluation
    2. 4.2 Current Measurement
      1. 4.2.1 Current Measurement

2.1.1 Power Domains and Power Modes

To realize different power levels, two core power domains are provided on the device: PD1 and PD0 and five operating modes (power modes) are provided to optimize the device power decreasing power: RUN, SLEEP, STOP, STANDBY, and SHUTDOWN. Figure 2-1 indicates what domains are available in each operating mode of the device.

GUID-E7556775-A599-4850-850B-CA74B70423B4-low.jpg Figure 2-1 MSPM0Gxx Operating Modes

Table 2-1 gives a more detailed list of the supported functionality in each operating mode. Users can choose the working conditions of the application according to the clock frequency, wake sources, CPU and peripherals requirements.

Abbreviations used in Table 2-1:

EN: The function is enabled in the specified mode.

DIS: The function is disabled in the specified mode, but the function's configuration is retained.

OPT: The function is optional in the specified mode, and remains enabled if configured to be enabled.

NS: The function is not automatically disabled in the specified mode, but its use is not supported.

OFF: The function is powered off in the specified mode, and no configuration information is retained.

Table 2-1 MSPM0Gxx Supported Functionality by Operating Mode
Operating Mode RUN SLEEP STOP STANDBY SHUTDOWN
RUN0 RUN1 RUN2 SLEEP0 SLEEP1 SLEEP2 STOP0 STOP1 STOP2 STANDBY0 STANDBY1
Oscillators SYSOSC EN EN DIS EN EN DIS OPT EN DIS DIS DIS OFF
LFOSC or LFXT EN (LFOSC or LFXT) OFF
HFXT OPT DIS DIS OPT DIS DIS DIS DIS DIS DIS DIS OFF
SYSPLL OPT DIS DIS OPT DIS DIS DIS DIS DIS DIS DIS OFF
Clocks CPUCLK 80 MHz max 32 kHz 32 kHz DIS OFF
MCLK to PD1 80 MHz max 32 kHz 32 kHz 80 MHz max 32 kHz

32 kHz

DIS

 OFF
ULPCLK to PD0 40 MHz max 32 kHz 32 kHz 40 MHz max 32 kHz

32 kHz

 4 MHz max 4 MHz 32 kHz DIS OFF
ULPCLK to TIMG0/1 40 MHz max 32 kHz 32 kHz 40 MHz max 32 kHz 32 kHz 4 MHz max 4 MHz 32 kHz OFF
RTCCLK 32 kHz OFF
MFCLK OPT DIS OPT DIS OPT DIS OFF
MFPCLK OPT DIS OPT DIS OPT DIS OFF
LFCLK 32 kHz DIS OFF
LFCLK to TIMG0/1 32 kHz OFF
LFCLK Monitor OPT OFF
MCLK Monitor OPT DIS OFF
PMU POR monitor EN
BOR monitor EN OFF
Core regulator FULL DRIVE REDUCED DRIVE LOW DRIVE OFF
Core Functions CPU EN DIS OFF
DMA OPT DIS (triggers supported) OFF
Flash EN DIS OFF
SRAM EN DIS OFF
Peripherals

PD1 Peripherals

 OPT DIS OFF

PD0 Peripherals

 OPT

OPT

 OFF
Analog TRNG OPT OFF
ADC OPT NS (triggers supported) OFF
12-bit DAC OPT NS OFF
OPA OPT NS OPT NS OPT NS OFF
GPAMP OPT NS OFF
COMP / 8-bit DAC OPT OPT (ULP only) OPT OPT (ULP only) OPT OPT (ULP only) OFF
IOMUX and IO Wakeup EN DIS w/ WAKE
Wake Sources N/A ANY IRQ PD0 IRQ IOMUX, NRST