SLAAEB9 February   2024 MSPM0G1505 , MSPM0G1506 , MSPM0G1507 , MSPM0G3505 , MSPM0G3505-Q1 , MSPM0G3506 , MSPM0G3506-Q1 , MSPM0G3507 , MSPM0G3507-Q1

 

  1.   1
  2. 1Description
  3. 2Required Peripherals
  4. 3Compatible Devices
  5. 4Design Steps
  6. 5Design Considerations
  7. 6Software Flow Chart
  8. 7Application Code
  9. 8Additional Resources
  10. 9E2E

1 Description

This subsystem demonstrates how the internal ADC, and math accelerator (MATHACL) modules within the MSPM0G family of devices can be used to implement a simple, streaming IIR filter of an analog signal. In this configuration, noise on an analog signal is filtered using a single pole IIR filter. The defined beta value can be adjusted to control the IIR filter decay over frequency.

GUID-20240122-SS0I-MTJQ-R7LG-RWV6HG2WR5DF-low.svg Figure 1-1 IIR Filter Functional Block Diagram