SLAAEF9 November 2023 MSPM0L1306
The MSPM0 family is based on the ARM Cortex M0+ CPU core architecture. The RL78 family is based on their own RL78 CPU core architecture. Table 3-1 gives an overview of the general features of the CPU in the MSPM0 family compared to the RL78.
Features | RL78 | MSPM0G | MSPM0L | MSPM0C |
---|---|---|---|---|
Architecture | Private RL78 core | Arm Cortex M0+ | ARM Cortex M0+ | Arm Cortex M0+ |
Instruction set | CISC | RISC | RISC | RISC |
Pipeline | 3-stage | 2-stage | 2-stage | 2-stage |
Operating Freq (Max) | 40 MHz | 80 MHz | 32 MHz | 24 MHz |
DMA | Yes | Yes | Yes | Yes |
Coremark/MHz | 1.5952 (1) | 2.39 (2) | 2.39 (2) | 2.39 (2) |