SLAAEG3 August   2024 TAC5111-Q1 , TAC5212-Q1 , TAC5311-Q1 , TAC5312-Q1 , TAC5411-Q1 , TAC5412-Q1 , TAD5212-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Signal Chain Architecture
  6. 3ASI Configuration for ICLA
  7. 4Decision Tree
  8. 5Application Example
    1. 5.1 Application Example Script
  9. 6Summary
  10. 7References

3 ASI Configuration for ICLA

The ASI buses of multiple TAX5XXX-Q1 devices are connected together through the digital output pin (DOUT) of each corresponding device. When ICLA is enabled, DOUT is a bidirectional transmitter and receiver for changes made within the limiter bank. The ICLA algorithm is mapped to transmit the data to other devices in the PASI_TX_CH8_CFG (P0_R37_D5) register and receive data from other devices in the PASI_RX_CH[6-8]_CFG (P0_R45-R47_D6:5) registers. The slot assignment for each channel is configured in the PASI_TX_CHx_CFG (P0_R30-R37_D4:0) and PASI_RX_CHx_CFG(P0_R40-R47_D4:0). Figure 3-1 shows an example slot configuration for four devices configured for ICLA.

Four Device Slot Configuration for ICLA Figure 3-1 Four Device Slot Configuration for ICLA