SLAAEG6A November   2023  – September 2024 TAA5212 , TAA5242 , TAA5412-Q1 , TAC5111 , TAC5111-Q1 , TAC5112 , TAC5112-Q1 , TAC5211 , TAC5212 , TAC5212-Q1 , TAC5311-Q1 , TAC5312-Q1 , TAC5411-Q1 , TAC5412-Q1 , TAD5112 , TAD5112-Q1 , TAD5142 , TAD5212 , TAD5212-Q1 , TAD5242

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Operating Modes for the Clocking
    1. 2.1 Automatic Modes of Operation
  6. 3Clocking Modes
    1. 3.1 Auto Primary BCLK Ratio
    2. 3.2 Auto Secondary BCLK Ratio
    3. 3.3 Auto MCLK Ratio
    4. 3.4 Auto MCLK Fixed
    5. 3.5 Custom Mode and Semi Automatic Mode of Operation
      1. 3.5.1 Semi-Automatic Mode
    6. 3.6 Additional Clocks
      1. 3.6.1 PDM Clocks
      2. 3.6.2 Boost Clock
      3. 3.6.3 SAR Clock
      4. 3.6.4 CLKOUT
  7. 4Clocking in Hardware Controlled Devices
  8. 5Revision History

3.6.4 CLKOUT

Internal clocks can be routed externally to a GPIO/GPO. The following registers are used to select the clock source as well as the divider ratio.

The possible input sources that can be routed to CLKOUT include:

  • DSP_CLK,SASI_BCLK,PASI_BCLK,OSC_CLK,MCLK ,CLK_SYS.

Note that OSC_CLK is 12.288Mhz.

Table 3-13 Register Settings for CLKOUT
Mode Configuration
CLKOUT_CLK_SEL (B0_P3_R70[2:0]),
CLKOUT_DIV_EN (B0_P3_R71[7])
CLKOUT_DIV (B0_P3_R71[6:0])