SLAAEI4 August   2024 TAC5111-Q1 , TAC5212-Q1 , TAC5311-Q1 , TAC5312-Q1 , TAC5411-Q1 , TAC5412-Q1 , TAD5212-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Signal Processing Chain
  6. 3Distortion Limiter
    1. 3.1 Distortion Limiter Parameters
      1. 3.1.1 Threshold Maximum
      2. 3.1.2 Threshold Minimum
      3. 3.1.3 Inflection Point
      4. 3.1.4 Slope
      5. 3.1.5 Attack Rate
      6. 3.1.6 Release Rate
      7. 3.1.7 Hold Counter
    2. 3.2 Limiter Response
  7. 4Brown-Out Protection
    1. 4.1 Brown-Out Protection Parameters
      1. 4.1.1 Critical Level
      2. 4.1.2 Gain Level
      3. 4.1.3 Attack Rate
      4. 4.1.4 Release Rate
      5. 4.1.5 Hold Counter
    2. 4.2 Brown-Out Protection Response
  8. 5Thermal Foldback
    1. 5.1 Thermal Foldback Parameters
      1. 5.1.1 Temperature Threshold
      2. 5.1.2 Maximum Attenuation Threshold
      3. 5.1.3 Slope
      4. 5.1.4 Attack Coefficient
      5. 5.1.5 Release Coefficient
      6. 5.1.6 Hold Counter
        1. 5.1.6.1 Thermal Foldback Response
  9. 6Example
  10. 7Summary
  11. 8References

2 Signal Processing Chain

The Limiter Bank algorithm is a digital signal design present in the DAC signal path of the TAx5xxx-Q1 devices. This algorithm governs the Distortion Limiter, Brown-out Protector, and Thermal Foldback feature (Figure 2-1).

DAC Signal Chain Figure 2-1 DAC Signal Chain

The left and right DAC channel signal levels are the inputs to the limiter bank. The user can select which signal is altered by the Distortion Limiter in the LIMITER_CFG (P1_R35_D6:7) register. The input MUX to the limiter bank can be configured to receive the max signal present, the left signal of the DAC channel, the right signal of the DAC channel, or the average signal level of both channels.

The limiter bank algorithm monitors the VBAT pin level and internal temperature of the die to apply changes to the left and right DAC channel output signal level. The user can activate or deactivate the Distortion Limiter, Brown-out Protector (BOP), and Thermal Foldback feature individually within the MISC_CFG0 register (P1_45).

The Distortion Limiter and BOP apply an attenuation to the output signal if VBAT is below the target level. These algorithms engage within the limiter bank as a function of VBAT, the default configuration, or AVDD by configuring the MISC_CFG0 (P1_R45_D1) and DIAG_CFG13 (P1_R83_D2) registers. Thermal Foldback attenuates the output signal if the temperature of the die exceeds the threshold governed by the coefficients on page 26 of the register map. Moreover, the limiter bank uses a small step-size during attack and release of the algorithm to reduce distortions in the input and output signal.

The limiter bank then applies the minimum of all gain adjustments made to the output signal of the DAC. The gain adjustments can be applied to both output channels, either channel individually, or none at all in the LIMITER_CFG (P1_R35_D4:5) register.

Limiter Bank Signal Chain Figure 2-2 Limiter Bank Signal Chain