SLAAEI4 August   2024 TAC5111-Q1 , TAC5212-Q1 , TAC5311-Q1 , TAC5312-Q1 , TAC5411-Q1 , TAC5412-Q1 , TAD5212-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Signal Processing Chain
  6. 3Distortion Limiter
    1. 3.1 Distortion Limiter Parameters
      1. 3.1.1 Threshold Maximum
      2. 3.1.2 Threshold Minimum
      3. 3.1.3 Inflection Point
      4. 3.1.4 Slope
      5. 3.1.5 Attack Rate
      6. 3.1.6 Release Rate
      7. 3.1.7 Hold Counter
    2. 3.2 Limiter Response
  7. 4Brown-Out Protection
    1. 4.1 Brown-Out Protection Parameters
      1. 4.1.1 Critical Level
      2. 4.1.2 Gain Level
      3. 4.1.3 Attack Rate
      4. 4.1.4 Release Rate
      5. 4.1.5 Hold Counter
    2. 4.2 Brown-Out Protection Response
  8. 5Thermal Foldback
    1. 5.1 Thermal Foldback Parameters
      1. 5.1.1 Temperature Threshold
      2. 5.1.2 Maximum Attenuation Threshold
      3. 5.1.3 Slope
      4. 5.1.4 Attack Coefficient
      5. 5.1.5 Release Coefficient
      6. 5.1.6 Hold Counter
        1. 5.1.6.1 Thermal Foldback Response
  9. 6Example
  10. 7Summary
  11. 8References

3.1.6 Release Rate

The release rate is the step rate response when the Distortion Limiter triggers a gain increase. The settling time of the signal is faster as this user-defined rate increases. This threshold is controlled by the coefficient YRAM_REL_COEFFI_LIM. Equation 6 shows how to compute the parameters from the desired attenuation rate in dB/step. The threshold range is from -1x10^6dB/step to 6dB/step and can be programmed in steps of 1x10^-6dB, where RR is the Release Rate of the output signal in dB/step.

Equation 6. YRAM_REL_COEFFI_LIM = round(10(RR/20)×230)

Table 3-7 lists the registers corresponding to YRAM_REL_COEFFI_LIM. The default value (0x40BDB7C0) corresponds to 0.1dB/step.

Table 3-7 Programmable Coefficient Registers for Release Rate
CoefficientPageRegisterReset ValueDescription
YRAM_REL_COEFFI_LIM0x190x640x00ADC_CH4_SF1_BYT1[31:24]
YRAM_REL_COEFFI_LIM0x190x650x00ADC_CH4_SF1_BYT2[23:16]
YRAM_REL_COEFFI_LIM0x190x660x00ADC_CH4_SF1_BYT3[15:8]
YRAM_REL_COEFFI_LIM0x190x670x00ADC_CH4_SF1_BYT4[7:0]