SLAAEJ0 November   2023 AM625 , MSPM0L1306

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
    1. 1.1 SPI Transaction Dataflow
    2. 1.2 AM62x Processor
    3. 1.3 MSPM0L130x Microcontroller
  5. 2Hardware Setup
    1. 2.1 A53 Core Hardware Setup
    2. 2.2 M4F Core Hardware Setup
  6. 3Software Setup
    1. 3.1 Cloning the Beyond SDK GitHub Repository
    2. 3.2 SK-AM62x Software Setup
      1. 3.2.1 A53 Core
      2. 3.2.2 M4F Core
    3. 3.3 LP-MSPM0L130x Software Setup
  7. 4Steps for Execution
    1. 4.1 Run Project on LP-MSPM0L130x
    2. 4.2 Run Project on SK-AM62x
      1. 4.2.1 A53 Core
      2. 4.2.2 M4F Core
  8. 5Results
    1. 5.1 Single Byte Single Channel
    2. 5.2 Single Byte Multi Channel
    3. 5.3 Multi Byte Single Channel
    4. 5.4 Multi Byte Multi Channel
  9. 6Summary
  10. 7References

1.2 AM62x Processor

AM62x Processor

The AM62x Sitara Microprocessor, shown in Figure 1-2, is a heterogeneous processor designed for a wide variety of embedded applications. SPI can be enabled through MAIN domain on A53 Core. Figure 1-2 shows a simplified block diagram for AM62x.

For more details, see AM62x Sitara Processors Data Sheet.

GUID-5052FCAC-AA21-430B-93CB-985567912F59-low.pngFigure 1-2 AM62x Simplified Block Diagram.