SLAAEM7 September   2024 TAS2120 , TAS2320

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Application Schematics
    1. 2.1 Recommended Component Ratings
    2. 2.2 Reference Schematic
  6. 3Design Guidelines
    1. 3.1  VDD Pin
    2. 3.2  PVDD Pin
    3. 3.3  GREG Pin
    4. 3.4  SW Pin
    5. 3.5  VBAT Pin
    6. 3.6  OUT_P and OUT_N Pins
      1. 3.6.1 Optional EMI Filter on Output
    7. 3.7  IOVDD Pin
    8. 3.8  DREG Pin
    9. 3.9  Digital I/O Pins
    10. 3.10 Ground Pins
    11. 3.11 HW Selection Pins
  7. 4EMI Specific Guidelines
  8. 5Summary
  9. 6References

3.8 DREG Pin

The DREG pin corresponds to an internally generated LDO voltage. The DREG pin acts as a power supply for the internal digital blocks of the device. The following guidelines need to be taken into consideration while routing the DREG pin on to the PCB:

  • The DREG pin must be decoupled to the GND pin with a capacitor of value ≥ 1µF. This capacitor needs to be placed as close to the device as possible. Use a 0201 capacitor to minimize ESR and ESL.
  • The DREG pin must not be loaded by any external circuit.
  • If decoupling through the ground plane of the PCB, use multiple vias to minimize parasitic inductance between the ground connection of the capacitor and the GND pin of the device.
Placement of DREG Decoupling CapacitorFigure 3-16 Placement of DREG Decoupling Capacitor