SLAAEN7 September   2024 MSPM0G1507 , MSPM0G3105 , MSPM0G3105-Q1 , MSPM0G3106 , MSPM0G3106-Q1 , MSPM0G3107 , MSPM0G3107-Q1 , MSPM0G3505 , MSPM0G3505-Q1 , MSPM0G3506 , MSPM0G3506-Q1 , MSPM0G3507 , MSPM0G3507-Q1 , MSPM0G3519 , MSPM0L1105 , MSPM0L1106 , MSPM0L1227 , MSPM0L1228 , MSPM0L1228-Q1 , MSPM0L1303 , MSPM0L1304 , MSPM0L1304-Q1 , MSPM0L1305 , MSPM0L1305-Q1 , MSPM0L1306 , MSPM0L1306-Q1 , MSPM0L1343 , MSPM0L1344 , MSPM0L1345 , MSPM0L1346 , MSPM0L2227 , MSPM0L2228 , MSPM0L2228-Q1

 

  1.   1
  2. 1 Description
  3. 2 Required Peripherals
  4. 3 Compatible Devices
  5. 4 Design Steps
  6. 5 Design Considerations
  7. 6 Software Flow Chart
  8. 7 Device Configuration
  9. 8 Application Code
  10. 9 Additional Resources
  11. 10E2E
  12. 11Trademarks

1 Description

This subsystem example in Figure 1-1 demonstrates how to set up the internal comparator and timers within the MSPM0L and MSPM0G family of devices to implement a simple frequency detector. The capture period can be configured to allow for various ranges of frequencies.

Subsystem Functional Block DiagramFigure 1-1 Subsystem Functional Block Diagram