SN65HVS885 34-V Digital-Input Serializer for 5-V Systems
- SLAS638A January 2009 – October 2015
  
  PRODUCTION DATA.

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DATA SHEET

SN65HVS885 34-V Digital-Input Serializer for 5-V Systems

1 Features

Eight Digital Sensor Inputs
- High Input Voltage up to 34 V
- Selectable Debounce Filters From 0 ms to
  3 ms
- Flexible Input Current-Limited – 0.2 mA to 5.2 mA
- Field Inputs Protected to 15-kV ESD
Single 5-V Supply
Output Drivers for External Status LEDs
Cascadable for More Inputs in Multiples of Eight
SPI-Compatible Interface
Overtemperature Indicator

2 Applications

Industrial PCs
Digital I/O Cards
High Channel Count Digital Input Modules
Decentralized I/O Modules

3 Description

The SN65HVS885 is an eight channel, digital-input serializer for high-channel density digital input modules in industrial and building automation. Operating from a 5-V supply the device accepts field input voltages of up to 34 V. In combination with galvanic isolators the device completes the interface between the high voltage signals on the field-side and the low-voltage signals on the controller side. Inputs signals are current limited and then validated by internal debounce filters.

With the addition of few external components, the input switching characteristic can be configured in accordance with IEC61131-2 for Type 1, 2 and 3 sensor switches.

Upon the application of load and clock signals, input data is latched in parallel into the shift register and afterwards clocked out serially.

Cascading of multiple devices is possible by connecting the serial output of the leading device with the serial input of the following device, enabling the design of high-channel count input modules. Multiple devices can be cascaded through a single serial port, reducing both the isolation channels and controller inputs required.

Input status can be visually indicated via constant current LED outputs. The current limit on the inputs is set by a single, external, precision resistor. An on-chip temperature sensor provides diagnostic information for graceful shutdown and system safety.

The SN65HVS885 is available in a 28-pin PWP PowerPAD™ package, allowing for efficient heat dissipation. The device is specified for operation at temperatures from –40°C to 125°C.

Device Information⁽¹⁾

PART NUMBER	PACKAGE	BODY SIZE (NOM)
SN65HVS885	HTSSOP (28)	9.70 mm × 4.40 mm

For all available packages, see the orderable addendum at the end of the datasheet.

Simplified I/O Structure

4 Revision History

Changes from * Revision (January 2009) to A Revision

Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section Go

5 Pin Configuration and Functions

PWP Package

28-Pin HTSSOP With Exposed Thermal Pad

Top View

Pin Functions

PIN		DESCRIPTION
NAME	NO.	DESCRIPTION
CE	24	Clock Enable Input
CLK	25	Serial Clock Input
DB0	1	Debounce select inputs
DB1	2	Debounce select inputs
GND	28	Device Ground
HOT	16	Over-Temperature Flag
IPx	3, 5, 7, 9, 11, 18, 20, 22	Input Channel x
LD	26	Load Pulse Input
NC	14	Not Connected
REx	4, 6, 8, 10, 12, 17, 19, 21	Return Path x (LED drive)
RLIM	13	Current Limiting Resistor
SIP	27	Serial Data Input
SOP	23	Serial Data Output
V_CC	15	5 V Device Supply

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted) ⁽¹⁾

			MIN	MAX	UNIT
V_CC	Device power input	V_CC	–0.5	6	V
V_IPx	Field digital inputs	IPx	–0.3	36	V
V_ID	Voltage at any logic input	DB0, DB1, CLK, SIP, CE, LD	–0.5	6	V
I_O	Output current	HOT, SOP	–8	8	mA
P_TOT	Continuous total power dissipation		See Thermal Information
T_J	Junction temperature			170	°C
T_stg	Storage temperature			150	°C

(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

				VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾	All pins	±4000	V
		Human body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾	IPx	±15000
		Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾		±1000
		Machine model (MM)⁽³⁾		±100

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

(3) JEDEC Standard 22, Method A115-A

6.3 Recommended Operating Conditions

		MIN	NOM	MAX	UNIT
V_CC	Device supply voltage	4.5	5	5.5	V
V_IPL	Field input low-state input voltage	0		4	V
V_IPH	Field input high-state input voltage	5.5		34	V
V_IL	Logic low-state input voltage	0		0.8	V
V_IH	Logic high-state input voltage	2.0		5.5	V
R_LIM	Current limiter resistor	17	25	500	kΩ
f_IP ⁽¹⁾	Input data rate	0		1	Mbps
T_A	Device	–40		125	°C
T_J	Junction Temperature			150	°C

(1) Maximum data rate corresponds to 0 ms debounce time, (DB0 = open, DB1 = GND), and R_IN = 0 Ω

6.4 Thermal Information

THERMAL METRIC⁽¹⁾			SN65HVS885	UNIT
			PWP (HTSSOP)
			28 PINS
R_θJA	Junction-to-ambient thermal resistance	High-K thermal resistance	35	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance		4.27	°C/W
R_θJB	Junction-to-board thermal resistance		15	°C/W
ψ_JT	Junction-to-top characterization parameter		0.6	°C/W
ψ_JB	Junction-to-board characterization parameter		15.9	°C/W
R_θJC(bot)	Junction-to-case (bottom) thermal resistance		2.4	°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

6.5 Electrical Characteristics

over full-range of recommended operating conditions (unless otherwise noted) all voltages measured against device ground, see Figure 9

PARAMETER		TERMINAL	TEST CONDITIONS		MIN	TYP	MAX	UNIT
FIELD INPUTS
V_TH–(IP)	Low-level device input threshold voltage	IP0–IP7	R_LIM = 25 kΩ		4	4.3		V
V_TH+(IP)	High-level device input threshold voltage					5.2	5.5	V
V_HYS(IP)	Device input hysteresis					0.9		V
V_TH–(IN)	Low-level field input threshold voltage	Measured at field side of R_IN	4.5 V < V_CC < 5.5 V, R_IN = 1.2 kΩ ± 5%, R_LIM = 25 kΩ, T_A ≤ 125°C		6	8.4		V
V_TH+(IN)	High-level field input threshold voltage					9.4	10	V
V_HYS(IN)	Field input hysteresis					1		V
R_IP	Input resistance	IP0–IP7	3 V < V_IPx < 6 V, R_LIM = 25 kΩ		0.2	0.63	1.1	kΩ
I_IP-LIM	Input current limit	IP0–IP7	R_LIM = 25 kΩ		3.15	3.6	4	mA
t_DB	Debounce times of input channels	IP0–IP7	DB0 = open, DB1 = GND			0		ms
			DB0 = GND, DB1 = open			1
			DB0 = DB1 = open			3
I_RE-on	RE on-state current	RE0–RE7	R_LIM = 25 kΩ, RE_X = GND		2.8	3.15	3.5	mA
DEVICE SUPPLY
I_CC(VCC)	Supply current	V_CC	IP0 to IP7 = 24V, RE_X = GND, All logic inputs open			6.5	10	mA
LOGIC INPUTS AND OUTPUTS
V_OL	Logic low-level output voltage	SOP, HOT	I_OL = 20 μA				0.4	V
V_OH	Logic high-level output voltage	SOP, HOT	I_OH = –20 μA		4			V
I_IL	Logic input leakage current	DB0, DB1, SIP, LD, CE, CLK			–50		50	μA
T_OVER	Over-temperature indication					150		°C
T_SHDN	Shutdown temperature					170		°C
POWER DISSIPATION
P_D	Power Dissipation		V_CC = 5 V, R_IN = 0Ω, R_LIM = 25 kΩ, RE0 – RE7 = GND, f_CLK = 100 MHz	IP0-IP7 = 34 V		1100		mW
				IP0-IP7 = 24 V
				IP0-IP7 = 20 V
				IP0-IP7 = 12 V

6.6 Timing Requirements

over operating free-air temperature range (unless otherwise noted)

			MIN	MAX	UNIT
t_W1	CLK pulse width	See Figure 6	4		ns
t_W2	LD pulse width	See Figure 4	6		ns
t_SU1	SIP to CLK setup time	See Figure 7	4		ns
t_H1	SIP to CLK hold time	See Figure 7	2		ns
t_SU2	Falling edge to rising edge (CE to CLK) setup time	See Figure 8	4		ns
t_REC	LD to CLK recovery time	See Figure 5	2		ns
f_CLK	Clock pulse frequency	See Figure 6	DC	100	MHz

6.7 Switching Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MAX	UNIT
t_PLH1, t_PHL1	CLK to SOP	C_L = 15 pF, see Figure 6	10	ns
t_PLH2, t_PHL2	LD to SOP	C_L = 15 pF, see Figure 4	14	ns
t_r, t_f	Rise and fall times	C_L = 15 pF, see Figure 6	6	ns

6.8 Typical Characteristics

Figure 1. Typical Input Characteristics

Figure 2. Typical Current Limiter Variation vs Ambient Temperature

Figure 3. Typical Limiter Threshold Voltage Variation vs Ambient Temperature

7 Parameter Measurement Information

7.1 Waveforms

For the complete serial interface timing, refer to Figure 17.

SN65HVS885 pmi_parallelloadmode_las638.gif

Figure 4. Parallel – Load Mode

Figure 6. Serial – Shift Mode

Figure 8. Serial – Shift Mode

Figure 5. Serial – Shift Mode

Figure 7. Serial – Shift Mode

7.2 Signal Conventions

Figure 9. On/Off Threshold Voltage Measurements

8 Detailed Description

8.1 Overview

The SN65HVS885 is an 8 channel, digital input serializer which operates from a 5 V supply and accepts digital inputs of up to 34 V on the 8 channels (IP0-IP7). The device provides a serially shifted digital output with reduced voltage ranges of 0-5 V for applications in industrial and building automation systems. The SN65HVS885 meets JEDEC standards for ESD protection (refer to ESD Ratings), and is SPI compatible for interfacing with standard microcontrollers. The serializer operates in 2 fundamental modes: Load Mode and Shift mode. In Load mode, information from the field inputs is allowed to latch into the shift register. In Shift mode, the information stored in the parallel shift register can be serially shifted to the serial output (SOP). A detailed description of the functional modes is available in the Device Functional Modes section.

8.2 Functional Block Diagram

8.3 Feature Description

8.3.1 Digital Inputs

Figure 10. Digital Input Stage

Each digital input operates as a controlled current sink limiting the input current to a maximum value of I_LIM. The current limit is derived from the reference current via I_LIM = n × I_REF, and I_REF is determined by I_REF = V_REF/R_LIM. Thus, changing the current limit requires the change of R_LIM to a different value via: R_LIM = n × V_REF/I_LIM.

Inserting the actual values for n and V_REF gives: R_LIM = 90 V / I_LIM.

While the device is specified for a current limit of 3.6 mA, (via R_LIM = 25 kΩ), it is easy to lower the current limit to further reduce the power consumption. For example, for a current limit of 2.5 mA simply calculate:

Equation 1. SN65HVS885 eq_rlim_las592.gif

8.3.2 Debounce Filter

The HVS885 applies a simple analog/digital filtering technique to remove unintended signal transitions due to contact bounce or other mechanical effects. Any new input (either low or high) must be present for the duration of the selected debounce time to be latched into the shift register as a valid state.

The logic signal levels at the control inputs, DB0 and DB1 of the internal Debounce-Select logic determine the different debounce times listed in the following truth table.

Table 1. Debounce Times

DB1	DB0	FUNCTION
Open	Open	3 ms delay
Open	GND	1 ms delay
GND	Open	0 ms delay (Filter bypassed)
GND	GND	Reserved

Figure 11. Equivalent Input Diagram

8.3.3 Shift Register

The conversion from parallel input to serial output data is performed by an eight-channel, parallel-in serial-out shift register. Parallel-in access is provided by the internal inputs, PIP0–PIP7, that are enabled by a low level at the load input (LD). When clocked, the latched input data shift towards the serial output (SOP). The shift register also provides a clock-enable function.

Clocking is accomplished by a low-to-high transition of the clock (CLK) input while LD is held high and the clock enable (CE) input is held low. Parallel loading is inhibited when LD is held high. The parallel inputs to the register are enabled while LD is low independently of the levels of the CLK, CE, or serial (SIP) inputs.

Figure 12. Shift Register Logic Structure

Table 2. Function Table

INPUTS			FUNCTION
LD	CLK	CE	FUNCTION
L	X	X	Parallel load
H	X	H	No change
H	↑	L	Shift⁽¹⁾

(1) Shift = content of each internal register shifts towards serial outputs. Data at SIP is shifted into first register.

8.3.4 Temperature Sensor

An on-chip temperature sensor monitors the device temperature and signals a fault condition if the temperature exceeds a first trip point at 150°C by pulling the HOT output low. If the junction temperature continues to rise, passing a second trip point at 170 °C, all device outputs assume high impedance state.

A special condition occurs when the chip temperature exceeds the second temperature trip point due to an output short; the HOT output buffer becomes high impedance, thus separating the buffer from the external circuitry. An internal 100-kΩ pulldown resistor, connecting the HOT-pin to ground, is used as a "cooling down" resistor, which continues to provide a logic low level to the external circuitry.

8.4 Device Functional Modes

The 2 functional modes of operation are Load mode and Shift mode. Load mode enables information from the field inputs to latch into the shift register. To enter load mode, the LD pin must be held low, and the device will remain in load mode regardless of the CLK, CE, or serial (SIP) input levels. A high level at the LD pin switches the device into Shift mode. When the device is in Shift mode, a low level at the CE pin will cause the data stored in the parallel shift register to be serially shifted to the serial output (SOP) on the rising edge of CLK. A high level at the CE pin inhibits the serial shifting, which is demonstrated in Figure 17. After 8 consecutive CLK pulses, the serial output (SOP) will remain at the level of the serial input (SIP) which is internally pulled to logic high. A logic high at the CE pin is required to signify the end of the serial data output. In the case of a daisy chained configuration, the serial output (SOP) of the SN65HVS885 can be connected to the serial input (SIP) of a following device, and additional clock pulses are required to shift the additional data out of the chain. The number of consecutive clock pulses will equal 8 times the number of devices in the chain. See Figure 18 for an example of a cascaded chain of 4x SN65HVS885.