SLAS988B June   2014  – August 2015 TAS5756M

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
    1. 6.1 Internal Pin Configurations
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics
    6. 7.6  MCLK Timing
    7. 7.7  Serial Audio Port Timing - Slave Mode
    8. 7.8  Serial Audio Port Timing - Master Mode
    9. 7.9  I2C Bus Timing - Standard
    10. 7.10 I2C Bus Timing - Fast
    11. 7.11 SPK_MUTE Timing
    12. 7.12 Power Dissipation
    13. 7.13 Typical Characteristics
      1. 7.13.1 Bridge Tied Load (BTL) Configuration Curves
      2. 7.13.2 Parallel Bridge Tied Load (PBTL) Configuration
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Power-on-Reset (POR) Function
      2. 8.3.2 Device Clocking
      3. 8.3.3 Serial Audio Port
        1. 8.3.3.1 Clock Master Mode from Audio Rate Master Clock
        2. 8.3.3.2 Clock Master from a Non-Audio Rate Master Clock
        3. 8.3.3.3 Clock Slave Mode with 4-Wire Operation (SCLK, MCLK, LRCK/FS, SDIN)
        4. 8.3.3.4 Clock Slave Mode with SLCK PLL to Generate Internal Clocks (3-Wire PCM)
          1. 8.3.3.4.1 Clock Generation using the PLL
          2. 8.3.3.4.2 PLL Calculation
            1. 8.3.3.4.2.1 Examples:
        5. 8.3.3.5 Serial Audio Port - Data Formats and Bit Depths
          1. 8.3.3.5.1 Data Formats and Master/Slave Modes of Operation
        6. 8.3.3.6 Input Signal Sensing (Power-Save Mode)
        7. 8.3.3.7 Serial Data Output
      4. 8.3.4 Modulation Scheme
        1. 8.3.4.1 BD-Modulation
      5. 8.3.5 miniDSP Audio Processing Engine
        1. 8.3.5.1 HybridFlow Architecture
        2. 8.3.5.2 Volume Control
          1. 8.3.5.2.1 Digital Volume Control
            1. 8.3.5.2.1.1 Emergency Volume Ramp Down
      6. 8.3.6 Adjustable Amplifier Gain and Switching Frequency Selection
      7. 8.3.7 Error Handling and Protection Suite
        1. 8.3.7.1 Device Overtemperature Protection
        2. 8.3.7.2 SPK_OUTxx Overcurrent Protection
        3. 8.3.7.3 DC Offset Protection
        4. 8.3.7.4 Internal VAVDD Undervoltage-Error Protection
        5. 8.3.7.5 Internal VPVDD Undervoltage-Error Protection
        6. 8.3.7.6 Internal VPVDD Overvoltage-Error Protection
        7. 8.3.7.7 External Undervoltage-Error Protection
        8. 8.3.7.8 Internal Clock Error Notification (CLKE)
      8. 8.3.8 GPIO Port and Hardware Control Pins
      9. 8.3.9 I2C Communication Port
        1. 8.3.9.1 Slave Address
        2. 8.3.9.2 Register Address Auto-Increment Mode
        3. 8.3.9.3 Packet Protocol
        4. 8.3.9.4 Write Register
        5. 8.3.9.5 Read Register
    4. 8.4 Device Functional Modes
      1. 8.4.1 Serial Audio Port Operating Modes
      2. 8.4.2 Communication Port Operating Modes
      3. 8.4.3 Audio Processing Modes via HybridFlow Audio Processing
      4. 8.4.4 Speaker Amplifier Operating Modes
        1. 8.4.4.1 Stereo Mode
        2. 8.4.4.2 Mono Mode
        3. 8.4.4.3 Bi-Amp Mode
        4. 8.4.4.4 Master and Slave Mode Clocking for Digital Serial Audio Port
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 External Component Selection Criteria
      2. 9.1.2 Component Selection Impact on Board Layout, Component Placement, and Trace Routing
      3. 9.1.3 Amplifier Output Filtering
      4. 9.1.4 Programming the TAS5756M
        1. 9.1.4.1 Resetting the TAS5756M registers and modules
        2. 9.1.4.2 Adaptive Mode and using CRAM buffers
    2. 9.2 Typical Applications
      1. 9.2.1 2.0 (Stereo BTL) System
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Step One: Hardware Integration
          2. 9.2.1.2.2 Step Two: HybridFlow Selection and System Level Tuning
          3. 9.2.1.2.3 Step Three: Software Integration
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Mono (PBTL) Systems
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
          1. 9.2.2.2.1 Step One: Hardware Integration
          2. 9.2.2.2.2 Step Two: HybridFlow Selection and System Level Tuning
          3. 9.2.2.2.3 Step Three: Software Integration
        3. 9.2.2.3 Application Specific Performance Plots for Mono (PBTL) Systems
      3. 9.2.3 2.1 (Stereo BTL + External Mono Amplifier) Systems
        1. 9.2.3.1 Basic 2.1 System (TAS5756M Device + Simple Digital Input Amplifier)
        2. 9.2.3.2 Advanced 2.1 System (Two TAS5756M devices)
        3. 9.2.3.3 Design Requirements
        4. 9.2.3.4 Detailed Design Procedure
          1. 9.2.3.4.1 Step One: Hardware Integration
          2. 9.2.3.4.2 Step Two: HybridFlow Selection and System Level Tuning
          3. 9.2.3.4.3 Step Three: Software Integration
        5. 9.2.3.5 Application Specific Performance Plots for 2.1 (Stereo BTL + External Mono Amplifier) Systems
      4. 9.2.4 2.2 (Dual Stereo BTL) Systems
        1. 9.2.4.1 Design Requirements
        2. 9.2.4.2 Detailed Design Procedure
          1. 9.2.4.2.1 Step One: Hardware Integration
          2. 9.2.4.2.2 Step Two: HybridFlow Selection and System Level Tuning
          3. 9.2.4.2.3 Step Three: Software Integration
        3. 9.2.4.3 Application Specific Performance Plots for 2.2 (Dual Stereo BTL) Systems
      5. 9.2.5 1.1 (Dual BTL, Bi-Amped) Systems
        1. 9.2.5.1 Design Requirements
        2. 9.2.5.2 Detailed Design Procedure
          1. 9.2.5.2.1 Step One: Hardware Integration
          2. 9.2.5.2.2 Step Two: HybridFlow Selection and System Level Tuning
          3. 9.2.5.2.3 Step Three: Software Integration
        3. 9.2.5.3 Application Specific Performance Plots for 1.1 (Dual BTL, Bi-Amped) Systems
  10. 10Power Supply Recommendations
    1. 10.1 Power Supplies
      1. 10.1.1 DVDD Supply
      2. 10.1.2 PVDD Supply
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 General Guidelines for Audio Amplifiers
      2. 11.1.2 Importance of PVDD Bypass Capacitor Placement on PVDD Network
      3. 11.1.3 Optimizing Thermal Performance
        1. 11.1.3.1 Device, Copper, and Component Layout
        2. 11.1.3.2 Stencil Pattern
          1. 11.1.3.2.1 PCB footprint and Via Arrangement
            1. 11.1.3.2.1.1 Solder Stencil
    2. 11.2 Layout Example
      1. 11.2.1 2.0 (Stereo BTL) System
      2. 11.2.2 Mono (PBTL) System
      3. 11.2.3 2.1 (Stereo BTL + Mono PBTL) Systems
      4. 11.2.4 2.2 (Dual Stereo BTL) Systems
      5. 11.2.5 1.1 (Bi-Amped BTL) Systems
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Device Nomenclature
      2. 12.1.2 Development Support
    2. 12.2 Community Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

4 Revision History

Changes from A Revision (January 2015) to B Revision

Changes from * Revision (June 2014) to A Revision