SLASEA6D February   2017  – June 2020

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     32x6 MHz 256-QAM Carriers
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics - DC Specifications
    6. 7.6  Electrical Characteristics - Digital Specifications
    7. 7.7  Electrical Characteristics - AC Specifications
    8. 7.8  PLL/VCO Electrical Characteristics
    9. 7.9  Timing Requirements
    10. 7.10 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagrams
    3. 8.3 Feature Description
      1. 8.3.1  SerDes Inputs
      2. 8.3.2  SerDes Rate
      3. 8.3.3  SerDes PLL
      4. 8.3.4  SerDes Equalizer
      5. 8.3.5  JESD204B Descrambler
      6. 8.3.6  JESD204B Frame Assembly
      7. 8.3.7  SYNC Interface
      8. 8.3.8  Single or Dual Link Configuration
      9. 8.3.9  Multi-Device Synchronization
      10. 8.3.10 SYSREF Capture Circuit
      11. 8.3.11 SerDes Test Modes through Serial Programming
      12. 8.3.12 SerDes Test Modes through IEEE 1500 Programming
      13. 8.3.13 Error Counter
      14. 8.3.14 Eye Scan
      15. 8.3.15 JESD204B Pattern Test
      16. 8.3.16 Wideband DUC (wide-DUC)
      17. 8.3.17 Interpolation Block
        1. 8.3.17.1 Multi-DUC input
        2. 8.3.17.2 Interpolation Filters
        3. 8.3.17.3 JESD204B Modes, Interpolation and Clock phase Programming
        4. 8.3.17.4 Digital Quadrature Modulator
        5. 8.3.17.5 Low Power Coarse Resolution Mixing Modes
        6. 8.3.17.6 Inverse Sinc Filter
      18. 8.3.18 PA Protection Block
      19. 8.3.19 Gain Block
      20. 8.3.20 Output Summation
      21. 8.3.21 Output Delay
      22. 8.3.22 Polarity Inversion
      23. 8.3.23 Temperature Sensor
      24. 8.3.24 Alarm Monitoring
      25. 8.3.25 Differential Clock Inputs
      26. 8.3.26 CMOS Digital Inputs
      27. 8.3.27 DAC Fullscale Output Current
      28. 8.3.28 Current Steering DAC Architecture
      29. 8.3.29 DAC Transfer Function
    4. 8.4 Device Functional Modes
      1. 8.4.1 Clocking Modes
      2. 8.4.2 PLL Bypass Mode Programming
      3. 8.4.3 Internal PLL/VCO
      4. 8.4.4 CLKOUT
      5. 8.4.5 Serial Peripheral Interface (SPI)
        1. 8.4.5.1 NORMAL (RW)
        2. 8.4.5.2 WRITE_TO_CLEAR (W0C)
        3. 8.4.5.3 Writing to Reserved Bits
    5. 8.5 Register Maps
      1. 8.5.1  Chip Reset and Configuration Register (address = 0x00) [reset = 0x5803]
        1. Table 48. RESET_CONFIG Field Descriptions
      2. 8.5.2  IO Configuration Register (address = 0x01) [reset = 0x1800]
        1. Table 49. IO_CONFIG Field Descriptions
      3. 8.5.3  Lane Single Detect Alarm Mask Register (address = 0x02) [reset = 0xFFFF]
        1. Table 50. ALM_SD_MASK Field Descriptions
      4. 8.5.4  Clock Alarms Mask Register (address = 0x03) [reset = 0xFFFF
        1. Table 51. ALM_CLK_MASK Field Descriptions
      5. 8.5.5  SERDES Loss of Signal Detection Alarms Register (address = 0x04) [reset = variable]
        1. Table 52. ALM_SD_DET Field Descriptions
      6. 8.5.6  SYSREF Alignment Circuit Alarms Register (address = 0x05) [reset = variable]
        1. Table 53. ALM_SYSREF_DET Field Descriptions
      7. 8.5.7  Temperature Sensor and PLL Loop Voltage Register (address = 0x06) [reset = variable]
        1. Table 54. TEMP_PLLVOLT Field Descriptions
      8. 8.5.8  Page Set Register (address = 0x09) [reset = 0x0000]
        1. Table 55. PAGE_SET Field Descriptions
      9. 8.5.9  SYSREF Align to r1 and r3 Count Register (address = 0x78) [reset = 0x0000]
        1. Table 56. SYSREF_ALIGN_R Field Descriptions
      10. 8.5.10 SYSREF Phase Count 1 and 2 Register (address = 0x79) [reset = 0x0000]
        1. Table 57. SYSREF12_CNT Field Descriptions
      11. 8.5.11 SYSREF Phase Count 3 and 4 Register (address = 0x7A) [reset = 0x0000]
        1. Table 58. SYSREF34_CNT Field Descriptions
      12. 8.5.12 Vendor ID and Chip Version Register (address = 0x7F) [reset = 0x0009]
        1. Table 59. VENDOR_VER Field Descriptions
      13. 8.5.13 Multi-DUC Configuration (PAP, Interpolation) Register (address = 0x0A) [reset = 0x02B0]
        1. Table 60. MULTIDUC_CFG1 Field Descriptions
      14. 8.5.14 Multi-DUC Configuration (Mixers) Register (address = 0x0C) [reset = 0x2402]
        1. Table 61. MULTIDUC_CFG2 Field Descriptions
      15. 8.5.15 JESD FIFO Control Register (address = 0x0D)[reset = 0x8000]
        1. Table 62. JESD_FIFO Field Descriptions
      16. 8.5.16 Alarm Mask 1 Register (address = 0x0E) [reset = 0x00FF]
        1. Table 63. ALM_MASK1 Field Descriptions
      17. 8.5.17 Alarm Mask 2 Register (address = 0x0F) [reset = 0xFFFF]
        1. Table 64. ALM_MASK2 Field Descriptions
      18. 8.5.18 Alarm Mask 3 Register (address = 0x10) [reset = 0xFFFF]
        1. Table 65. ALM_MASK3 Field Descriptions
      19. 8.5.19 Alarm Mask 4 Register (address = 0x11) [reset = 0xFFFF]
        1. Table 66. ALM_MASK4 Field Descriptions
      20. 8.5.20 JESD Lane Skew Register (address = 0x12) [reset = 0x0000]
        1. Table 67. JESD_LN_SKEW Field Descriptions
      21. 8.5.21 CMIX Configuration Register (address = 0x17) [reset = 0x0000]
        1. Table 68. CMIX Field Descriptions
      22. 8.5.22 Output Summation and Delay Register (address = 0x19) [reset = 0x0000]
        1. Table 69. OUTSUM Field Descriptions
      23. 8.5.23 NCO Phase Path AB Register (address = 0x1C) [reset = 0x0000]
        1. Table 70. PHASE_NCOAB Field Descriptions
      24. 8.5.24 NCO Phase Path CD Register (address = 0x1D) [reset = 0x0000]
        1. Table 71. PHASE_NCOCD Field Descriptions
      25. 8.5.25 NCO Frequency Path AB Register (address = 0x1E-0x20) [reset = 0x0000 0000 0000]
        1. Table 72. FREQ_NCOAB Field Descriptions
      26. 8.5.26 NCO Frequency Path CD Register (address = 0x21-0x23) [reset = 0x0000 0000 0000]
        1. Table 73. FREQ_NCOCD Field Descriptions
      27. 8.5.27 SYSREF Use for Clock Divider Register (address = 0x24) [reset = 0x0010]
        1. Table 74. SYSREF_CLKDIV Field Descriptions
      28. 8.5.28 Serdes Clock Control Register (address = 0x25) [reset = 0x7700]
        1. Table 75. SERDES_CLK Field Descriptions
      29. 8.5.29 Sync Source Control 1 Register (address = 0x27) [reset = 0x1144]
        1. Table 76. SYNCSEL1 Field Descriptions
      30. 8.5.30 Sync Source Control 2 Register (address = 0x28) [reset = 0x0000]
        1. Table 77. SYNCSEL2 Field Descriptions
      31. 8.5.31 PAP path AB Gain Attenuation Step Register (address = 0x29) [reset = 0x0000]
        1. Table 78. PAP_GAIN_AB Field Descriptions
      32. 8.5.32 PAP path AB Wait Time Register (address = 0x2A) [reset = 0x0000]
        1. Table 79. PAP_WAIT_AB Field Descriptions
      33. 8.5.33 PAP path CD Gain Attenuation Step Register (address = 0x2B) [reset = 0x0000]
        1. Table 80. PAP_GAIN_CD Field Descriptions
      34. 8.5.34 PAP Path CD Wait Time Register (address = 0x2C) [reset = 0x0000]
        1. Table 81. PAP_WAIT_CD Field Descriptions
      35. 8.5.35 PAP path AB Configuration Register (address = 0x2D) [reset = 0x0FFF]
        1. Table 82. PAP_CFG_AB Field Descriptions
      36. 8.5.36 PAP path CD Configuration Register (address = 0x2E) [reset = 0x0FFF]
        1. Table 83. PAP_CFG_CD Field Descriptions
      37. 8.5.37 DAC SPI Configuration Register (address = 0x2F) [reset = 0x0000]
        1. Table 84. SPIDAC_TEST1 Field Descriptions
      38. 8.5.38 DAC SPI Constant Register (address = 0x30) [reset = 0x0000]
        1. Table 85. SPIDAC_TEST2 Field Descriptions
      39. 8.5.39 Gain for path AB Register (address = 0x32) [reset = 0x0400]
        1. Table 86. GAINAB Field Descriptions
      40. 8.5.40 Gain for path CD Register (address = 0x33) [reset = 0x0400]
        1. Table 87. GAINCD Field Descriptions
      41. 8.5.41 JESD Error Counter Register (address = 0x41) [reset = 0x0000]
        1. Table 88. JESD_ERR_CNT Field Descriptions
      42. 8.5.42 JESD ID 1 Register (address = 0x46) [reset = 0x0044]
        1. Table 89. JESD_ID1 Field Descriptions
      43. 8.5.43 JESD ID 2 Register (address = 0x47) [reset = 0x190A]
        1. Table 90. JESD ID 2 Register (JESD_ID2)
      44. 8.5.44 JESD ID 3 and Subclass Register (address = 0x48) [reset = 0x31C3]
        1. Table 91. JESD_ID3 Field Descriptions
      45. 8.5.45 JESD Lane Enable Register (address = 0x4A) [reset = 0x0003]
        1. Table 92. JESD_LN_EN Field Descriptions
      46. 8.5.46 JESD RBD Buffer and Frame Octets Register (address = 0x4B) [reset = 0x1300]
        1. Table 93. JESD_RBD_F Field Descriptions
      47. 8.5.47 JESD K and L Parameters Register (address = 0x4C) [reset = 0x1303]
        1. Table 94. JESD_K_L Field Descriptions
      48. 8.5.48 JESD M and S Parameters Register (address = 0x4D) [reset = 0x0100]
        1. Table 95. JESD_M_S Field Descriptions
      49. 8.5.49 JESD N, HD and SCR Parameters Register (address = 0x4E) [reset = 0x0F4F]
        1. Table 96. JESD_N_HD_SCR Field Descriptions
      50. 8.5.50 JESD Character Match and Other Register (address = 0x4F) [reset = 0x1CC1]
        1. Table 97. JESD_MATCH Field Descriptions
      51. 8.5.51 JESD Link Configuration Data Register (address = 0x50) [reset = 0x0000]
        1. Table 98. JESD_Link_CFG Field Descriptions
      52. 8.5.52 JESD Sync Request Register (address = 0x51) [reset = 0x00FF]
        1. Table 99. JESD_SYNC_REQ Field Descriptions
      53. 8.5.53 JESD Error Output Register (address = 0x52) [reset = 0x00FF]
        1. Table 100. JESD_ERR_OUT Field Descriptions
      54. 8.5.54 JESD ILA Check 1 Register (address = 0x53) [reset = 0x0100]
        1. Table 101. JESD_ILA_CFG1 Field Descriptions
      55. 8.5.55 JESD ILA Check 2 Register (address = 0x54) [reset = 0x8E60]
        1. Table 102. JESD_ILA_CFG2 Field Descriptions
      56. 8.5.56 JESD SYSREF Mode Register (address = 0x5C) [reset = 0x0001]
        1. Table 103. JESD_SYSR_MODE Field Descriptions
      57. 8.5.57 JESD Crossbar Configuration 1 Register (address = 0x5F) [reset = 0x0123]
        1. Table 104. JESD_CROSSBAR1 Field Descriptions
      58. 8.5.58 JESD Crossbar Configuration 2 Register (address = 0x60) [reset = 0x4567]
        1. Table 105. JESD_CROSSBAR2 Field Descriptions
      59. 8.5.59 JESD Alarms for Lane 0 Register (address = 0x64) [reset = 0x0000]
        1. Table 106. JESD_ALM_L0 Field Descriptions
      60. 8.5.60 JESD Alarms for Lane 1 Register (address = 0x65) [reset = 0x0000]
        1. Table 107. JESD_ALM_L1 Field Descriptions
      61. 8.5.61 JESD Alarms for Lane 2 Register (address = 0x66) [reset = 0x0000]
        1. Table 108. JESD_ALM_L2 Field Descriptions
      62. 8.5.62 JESD Alarms for Lane 3 Register (address = 0x67) [reset = 0x0000]
        1. Table 109. JESD_ALM_L3 Field Descriptions
      63. 8.5.63 JESD Alarms for Lane 4 Register (address = 0x68) [reset = 0x0000]
        1. Table 110. JESD_ALM_L4 Field Descriptions
      64. 8.5.64 JESD Alarms for Lane 5 Register (address = 0x69) [reset = 0x0000]
        1. Table 111. JESD_ALM_L5 Field Descriptions
      65. 8.5.65 JESD Alarms for Lane 6 Register (address = 0x6A [reset = 0x0000]
        1. Table 112. JESD_ALM_L6 Field Descriptions
      66. 8.5.66 JESD Alarms for Lane 7 Register (address = 0x6B) [reset = 0x0000]
        1. Table 113. JESD Alarms for Lane 7 Register (JESD_ALM_L7)
      67. 8.5.67 SYSREF and PAP Alarms Register (address = 0x6C) [reset = 0x0000]
        1. Table 114. ALM_SYSREF_PAP Field Descriptions
      68. 8.5.68 Clock Divider Alarms 1 Register (address = 0x6D) [reset = 0x0000]
        1. Table 115. ALM_CLKDIV1 Field Descriptions
      69. 8.5.69 Clock Configuration Register (address = 0x0A) [reset = 0xFC03]
        1. Table 116. CLK_CONFIG Field Descriptions
      70. 8.5.70 Sleep Configuration Register (address = 0x0B) [reset = 0x0022]
        1. Table 117. SLEEP_CONFIG Field Descriptions
      71. 8.5.71 Divided Output Clock Configuration Register (address = 0x0C) [reset = 0x2002]
        1. Table 118. CLK_OUT Field Descriptions
      72. 8.5.72 DAC Fullscale Current Register (address = 0x0D) [reset = 0xF000]
        1. Table 119. DACFS Field Descriptions
      73. 8.5.73 Internal SYSREF Generator Register (address = 0x10) [reset = 0x0000]
        1. Table 120. LCMGEN Field Descriptions
      74. 8.5.74 Counter for Internal SYSREF Generator Register (address = 0x11) [reset = 0x0000]
        1. Table 121. LCMGEN_DIV Field Descriptions
      75. 8.5.75 SPI SYSREF for Internal SYSREF Generator Register (address = 0x12) [reset = 0x0000]
        1. Table 122. LCMGEN_SPISYSREF Field Descriptions
      76. 8.5.76 Digital Test Signals Register (address = 0x1B) [reset = 0x0000]
        1. Table 123. DTEST Field Descriptions
      77. 8.5.77 Sleep Pin Control Register (address = 0x23) [reset = 0xFFFF]
        1. Table 124. SLEEP_CNTL Field Descriptions
      78. 8.5.78 SYSREF Capture Circuit Control Register (address = 0x24) [reset = 0x1000]
        1. Table 125. SYSR_CAPTURE Field Descriptions
      79. 8.5.79 Clock Input and PLL Configuration Register (address = 0x31) [reset = 0x0200]
        1. Table 126. Clock Input and PLL Configuration Register (CLK_PLL_CFG)
      80. 8.5.80 PLL Configuration 1 Register (address = 0x32) [reset = 0x0308]
        1. Table 127. CONFIG1 Field Descriptions
      81. 8.5.81 PLL Configuration 2 Register (address = 0x33) [reset = 0x4018]
        1. Table 128. PLL_CONFIG2 Field Descriptions
      82. 8.5.82 LVDS Output Configuration Register (address = 0x34) [reset = 0x0000]
        1. Table 129. LVDS_CONFIG Field Descriptions
      83. 8.5.83 Fuse Farm clock divider Register (address = 0x35) [reset = 0x0018]
        1. Table 130. PLL_FDIV Field Descriptions
      84. 8.5.84 Serdes Clock Configuration Register (address = 0x3B) [reset = 0x1802]
        1. Table 131. SRDS_CLK_CFG Field Descriptions
      85. 8.5.85 Serdes PLL Configuration Register (address = 0x3C) [reset = 0x8228]
        1. Table 132. SRDS_PLL_CFG Field Descriptions
      86. 8.5.86 Serdes Configuration 1 Register (address = 0x3D) [reset = 0x0x0088]
        1. Table 133. RDS_CFG1 Field Descriptions
      87. 8.5.87 Serdes Configuration 2 Register (address = 0x3E) [reset = 0x0x0909]
        1. Table 134. SRDS_CFG2 Field Descriptions
      88. 8.5.88 Serdes Polarity Control Register (address = 0x3F) [reset = 0x0000]
        1. Table 135. SRDS_POL Field Descriptions
      89. 8.5.89 JESD204B SYNCB OUTPUT Register (address = 0x76) [reset = 0x0000]
        1. Table 136. SYNCBOUT Field Descriptions
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Start-up Sequence
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Calculating the JESD204B SerDes rate
      4. 9.2.4 Calculating valid JESD204B SYSREF Frequency
      5. 9.2.5 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 Power Supply Sequencing
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Related Links
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

8.4.3 Internal PLL/VCO

The DAC38RF82 (or DAC38RF89) has an internal clock generation circuit consisting of a PLL and two selectable VCOs, as shown in Figure 49.

DAC38RF82 DAC38RF89 internal_PLL_VCO_block_diagram_SLASEA3.gifFigure 49. Internal PLL/VCO Block Diagram

DAC38RF82 (or DAC38RF89) each have a low VCO (VCO0) and high VCO (VCO1), but they are tuned to different center frequencies in each device. The VCO frequency ranges for each device are summarized in Electrical Characteristics - Digital Specifications. The VCO is selected through field PLL_VCOSEL in register PLL_CONFIG2 (8.5.81), with ‘0’ selecting the low VCO and a ‘1’ the high VCO. The 7 bit VCO tuning code in field PLL_VCO in register PLL_CONFIG2 (8.5.81) is used to tune the VCO frequency from the lowest frequency in the range to the highest frequency for the particular VCO used. For the low VCO the center VCO frequency is achieved with PLL_VCO = 63decimal and for the high VCO the center frequency is achieved with PLL_VCO = 63decimal.

The supply current, and therefore; the analog signal amplitude in the VCO is controlled using the field PLL_VCO_RDAC in register PLL_CONFIG1 (8.5.80). This control signal should be set 15decimal initially for 18 mA supply current in the VCO and ~1.4 VPP single ended oscillation amplitude.

The PLL has no prescaler, so the DAC sample rate is the VCO frequency. In the PLL feedback path a fixed ÷ 4 frequency divider block receives the VCO output clock and divides its frequency by 4. The maximum operating frequency of the phase-frequency detector (PFD) and charge pump (CP) requires this. The M (feedback) clock divider takes the output clock signal from the fixed ÷4 block and divides it by a programmable ratio set by the 8-bit field in field PLL_M_M1 in register PLL_CONFIG1 (8.5.80). The programmable division ratio range is ÷1 to ÷256, and is the value of the 8 bit unsigned binary code + 1. Although it is possible to program the M divider to ÷1, ÷2 and ÷3, these values should not be used. As stated previously the PFD and CP have a finite maximum operating frequency, which is the VCO frequency divided by the fixed divider ratio multiplied by the minimum allowable M divider ratio.

Equation 18. DAC38RF82 DAC38RF89 eq18_SLASEA3.gif

The N (reference) divider determines the ratio between the input reference clock frequency and the PFD operating frequency, and is set by the 5-bit field PLL_N_M1 in register CLK_PLL_CFG (8.5.79). The division ratio range is ÷1 to ÷32, and is the value of the 5-bit unsigned binary code + 1.

The charge pump output current amplitude is set using the 4-bit field PLL_CP_ADJ in in register PLL_CONFIG2 (8.5.81). The current amplitude is simply the digital code multiplied by the unit current amplitude of 100 µA. In a nominal condition, with the DAC38RF82 VCO0 running at 5.898 GHz, and with the M divider set to ÷4, the PFD will run at 368.625 MHz, and the change pump current should set to 6decimal, which gives 600 µA charge pump output current for a good phase margin of 69 degrees. If a higher M ratio (for lower PFD frequencies) are required the charge pump output current must be increased to maintain good loop stability and prevent excessive peaking in the phase noise response. The charge pump output current setting PLL_CP_ADJ should be adjusted in relation to the feedback (M) divider ratio PLL_M_M1 according to the following table to maintain a constant phase margin of 69 degrees.

Table 46. M vs Kp for Maintaining Good Stability

M CP_ADJ
4 6
6 9
8 12
10 15

Similarly for the DAC38RF82 VCO2 running at 8.847 GHz, and with the M divider set to ÷4, the PFD will run at 552.9375 MHz as shown above. Here the change pump current should set to 6decimal, which gives 600 µA charge pump output current for a good phase margin of 69 degrees.