SLASEJ5B October   2017  – January 2020

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Typical Application Schematic
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Device Enable (EN)
      2. 7.3.2 Gated Output (Gx)
      3. 7.3.3 Register Clear (CLR)
      4. 7.3.4 Open-Drain Outputs and Flexible Diagnostics Channel
        1. 7.3.4.1 Configurable Outputs
        2. 7.3.4.2 LED-Open Diagnostics
        3. 7.3.4.3 LED-Short Diagnostics
      5. 7.3.5 Thermal Shutdown
      6. 7.3.6 Command Error
      7. 7.3.7 Serial Communication Error
      8. 7.3.8 Error Feedback
      9. 7.3.9 Interface
        1. 7.3.9.1 Register Write
        2. 7.3.9.2 Register Read
        3. 7.3.9.3 Shift-Register Communication-Fault Detection
        4. 7.3.9.4 Clear Register
        5. 7.3.9.5 Register Clock
    4. 7.4 Device Functional Modes
      1. 7.4.1 Normal Operation
      2. 7.4.2 POR Reset
      3. 7.4.3 Standby Mode
    5. 7.5 Register Maps
    6. 7.6 Interface Registers
      1. 7.6.1 Configuration Register (Offset = 0h) [reset = 0h]
        1. Table 5. Configuration Register Field Descriptions
      2. 7.6.2 Fault Readback Register (Offset = 1h) [reset = 0h]
        1. Table 6. Fault Readback Register Field Descriptions
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Receiving Notification of Documentation Updates
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

5 Pin Configuration and Functions

PWP PowerPAD™ Package
28-Pin HTSSOP With Exposed Thermal Pad
Top View

Pin Functions

PIN I/O DESCRIPTION
NAME NO.
CLR 13 I Shift register clear, active-low. CLR low level clears all the storage registers in the device, shift registers work normally. CLR high level makes both storage registers and shift registers work normally.
DRAIN0 4 O Channel 0 open drain-output
DRAIN1/DIAG0 5 I/O Channel 1 open-drain output or diagnostics input 0
DRAIN2 6 O Channel 2 open drain output
DRAIN3/DIAG2 7 I/O Channel 3 open-drain output or diagnostics input 2
DRAIN4 8 O Channel 4 open drain output
DRAIN5/DIAG4 9 I/O Channel 5 open-drain output or diagnostics input 4
DRAIN6 10 O Channel 6 open-drain output
DRAIN7/DIAG6 11 I/O Channel 7 open-drain output or diagnostics input 6
DRAIN8 18 O Channel 8 open-drain output
DRAIN9/DIAG8 19 I/O Channel 9 open-drain output or diagnostics input 8
DRAIN10 20 O Channel 10 open-drain output
DRAIN11/DIAG10 21 I/O Channel 11 open-drain output or diagnostics input 10
DRAIN12 22 O Channel 12 open-drain output
DRAIN13/DIAG12 23 I/O Channel 13 open-drain output or diagnostics input 12
DRAIN14 24 O Channel 14 open-drain output
DRAIN15/DIAG14 25 I/O Channel 15 open-drain output or diagnostics input 14
EN 14 I Device enable, active-low. EN high level shuts down the device, all the registers reset, and the device enters standby mode. EN low level enables the device, all functions work normally.
ERR 27 O Open-drain error feedback
G1 2 I Channel enable, controls DRAIN0–DRAIN7 outputs, active-low
G2 3 I Channel enable, controls DRAIN8–DRAIN15 outputs, active-low
NC 26 NC No intenal connection
RCK 16 I Serial data latch. The data in each shift register transfers to a storage register at the rising edge of RCK. Meanwhile, the status bit is loaded to the shift register.
SER IN 12 I Serial data input. Data on SER IN loads into the shift register on each rising edge of SRCK.
SER OUT 15 O Serial data output. The purpose of this pin is to cascade several devices on the serial bus.
SRCK 17 I Serial clock input. On each rising SRCK edge, data transfers from SER IN to the internal serial shift registers.
VCC 1 P Power supply pin for the device. Add a 0.1-μF ceramic capacitor near the pin.
GND 28 G Power ground, the ground reference pin for the device. This pin must connect to the ground plane on the PCB.
Thermal pad — — Connect to polygon pour to optimize thermal performance