SLASEJ5B October 2017 – January 2020
PRODUCTION DATA.
The TLC6C5816-Q1 device provides a cyclic redundancy check to verify register values in the shift registers. In readback mode, the TLC6C5816-Q1 device provides 6 bits of the CRC remainder. The MCU can read back the CRC remainder and check if the remainder is correct. The CRC checksum provides a readback method to verify shift register values without altering them.
The TLC6C5816-Q1 device also checks the configuration register for faulty commands.
The TLC6C5816-Q1 configuration register consists of 24 bits. To generate the CRC checksum, the device first shifts left 6 bits and appends 0s, then bit-wise exclusive-ORs the 30 data bits with the polynomial to get the checksum.
For example, if the configuration data is 0xD7i0F68 and the polynomial is 0x43 (7’b100i0011), the CRC checksum is 0x19 (6’b01i1001).
The MCU can read back the CRC checksum and append it to the LSB of 24 bits, and then the 30 bits of data becomes 0x35C3 DA19. Performing the bit-wise exclusive-OR operation with the polynomial should lead to a residual of 0.
CRC reference: CRC Implementation With MSP430