SLAU144 User guide

SLAU144K December 2004 – August 2022 MSP430AFE221 , MSP430AFE222 , MSP430AFE223 , MSP430AFE231 , MSP430AFE232 , MSP430AFE233 , MSP430AFE251 , MSP430AFE252 , MSP430AFE253 , MSP430F2001 , MSP430F2002 , MSP430F2003 , MSP430F2011 , MSP430F2012 , MSP430F2013 , MSP430F2101 , MSP430F2111 , MSP430F2112 , MSP430F2121 , MSP430F2122 , MSP430F2131 , MSP430F2132 , MSP430F2132-EP , MSP430F2232 , MSP430F2234 , MSP430F2252 , MSP430F2252-Q1 , MSP430F2254 , MSP430F2272 , MSP430F2272-Q1 , MSP430F2274 , MSP430F2274-EP , MSP430F233 , MSP430F2330 , MSP430F235 , MSP430F2350 , MSP430F2370 , MSP430F2410 , MSP430F2416 , MSP430F2417 , MSP430F2418 , MSP430F2419 , MSP430F247 , MSP430F2471 , MSP430F248 , MSP430F2481 , MSP430F249 , MSP430F2491 , MSP430F2616 , MSP430F2617 , MSP430F2618 , MSP430F2619 , MSP430G2001 , MSP430G2101 , MSP430G2102 , MSP430G2111 , MSP430G2112 , MSP430G2121 , MSP430G2131 , MSP430G2132 , MSP430G2152 , MSP430G2153 , MSP430G2201 , MSP430G2201-Q1 , MSP430G2202 , MSP430G2203 , MSP430G2210 , MSP430G2211 , MSP430G2212 , MSP430G2213 , MSP430G2221 , MSP430G2230 , MSP430G2231 , MSP430G2231-Q1 , MSP430G2232 , MSP430G2233 , MSP430G2252 , MSP430G2253 , MSP430G2302 , MSP430G2303 , MSP430G2312 , MSP430G2313 , MSP430G2332 , MSP430G2333 , MSP430G2352 , MSP430G2353 , MSP430G2402 , MSP430G2403 , MSP430G2412 , MSP430G2413 , MSP430G2432 , MSP430G2433 , MSP430G2444 , MSP430G2452 , MSP430G2453 , MSP430G2513 , MSP430G2533 , MSP430G2544 , MSP430G2553 , MSP430G2744 , MSP430G2755 , MSP430G2855 , MSP430G2955 , MSP430TCH5E

*RLA[.W]

Rotate left arithmetically

*RLA.B

Rotate left arithmetically

Syntax

RLA dst or RLA.W dst 
RLA.B dst

Operation

C <- MSB <- MSB-1 .... LSB+1 <- LSB <- 0

Emulation

ADD dst,dst 
ADD.B dst,dst

Description

The destination operand is shifted left one position as shown in Figure 3-15. The MSB is shifted into the carry bit (C) and the LSB is filled with 0. The RLA instruction acts as a signed multiplication by 2.

An overflow occurs if dst ≥ 04000h and dst < 0C000h before operation is performed: the result has changed sign.

Figure 3-15 Destination Operand – Arithmetic Shift Left

An overflow occurs if dst ≥ 040h and dst < 0C0h before the operation is performed: the result has changed sign.

Status Bits

N: Set if result is negative, reset if positive

Z: Set if result is zero, reset otherwise

C: Loaded from the MSB

V: Set if an arithmetic overflow occurs:

the initial value is 04000h ≤ dst < 0C000h; reset otherwise

Set if an arithmetic overflow occurs:

the initial value is 040h ≤ dst < 0C0h; reset otherwise

Mode Bits

OSCOFF, CPUOFF,and GIE are not affected.

Example

R7 is multiplied by 2.

RLA     R7   ; Shift left R7  (x 2)

Example

The low byte of R7 is multiplied by 4.

RLA.B   R7   ; Shift left low byte of R7 (x 2) 
RLA.B   R7   ; Shift left low byte of R7 (x 4)

Note:

RLA Substitution

The assembler does not recognize the instruction:

RLA @R5+, RLA.B @R5+, or RLA(.B) @R5

It must be substituted by:

ADD @R5+,-2(R5), ADD.B @R5+,-1(R5), or ADD(.B) @R5