SLAU144K December 2004 – August 2022 MSP430AFE221 , MSP430AFE222 , MSP430AFE223 , MSP430AFE231 , MSP430AFE232 , MSP430AFE233 , MSP430AFE251 , MSP430AFE252 , MSP430AFE253 , MSP430F2001 , MSP430F2002 , MSP430F2003 , MSP430F2011 , MSP430F2012 , MSP430F2013 , MSP430F2101 , MSP430F2111 , MSP430F2112 , MSP430F2121 , MSP430F2122 , MSP430F2131 , MSP430F2132 , MSP430F2132-EP , MSP430F2232 , MSP430F2234 , MSP430F2252 , MSP430F2252-Q1 , MSP430F2254 , MSP430F2272 , MSP430F2272-Q1 , MSP430F2274 , MSP430F2274-EP , MSP430F233 , MSP430F2330 , MSP430F235 , MSP430F2350 , MSP430F2370 , MSP430F2410 , MSP430F2416 , MSP430F2417 , MSP430F2418 , MSP430F2419 , MSP430F247 , MSP430F2471 , MSP430F248 , MSP430F2481 , MSP430F249 , MSP430F2491 , MSP430F2616 , MSP430F2617 , MSP430F2618 , MSP430F2619 , MSP430G2001 , MSP430G2101 , MSP430G2102 , MSP430G2111 , MSP430G2112 , MSP430G2121 , MSP430G2131 , MSP430G2132 , MSP430G2152 , MSP430G2153 , MSP430G2201 , MSP430G2201-Q1 , MSP430G2202 , MSP430G2203 , MSP430G2210 , MSP430G2211 , MSP430G2212 , MSP430G2213 , MSP430G2221 , MSP430G2230 , MSP430G2231 , MSP430G2231-Q1 , MSP430G2232 , MSP430G2233 , MSP430G2252 , MSP430G2253 , MSP430G2302 , MSP430G2303 , MSP430G2312 , MSP430G2313 , MSP430G2332 , MSP430G2333 , MSP430G2352 , MSP430G2353 , MSP430G2402 , MSP430G2403 , MSP430G2412 , MSP430G2413 , MSP430G2432 , MSP430G2433 , MSP430G2444 , MSP430G2452 , MSP430G2453 , MSP430G2513 , MSP430G2533 , MSP430G2544 , MSP430G2553 , MSP430G2744 , MSP430G2755 , MSP430G2855 , MSP430G2955 , MSP430TCH5E
In addition to the MSP430 and MSP430X instructions, emulated instructions are instructions that make code easier to write and read, but do not have op-codes themselves. Instead, they are replaced automatically by the assembler with a core instruction. There is no code or performance penalty for using emulated instructions. The emulated instructions are listed in Table 4-7.
| Instruction | Explanation | Emulation | Status Bits (1) | |||
|---|---|---|---|---|---|---|
| V | N | Z | C | |||
ADC(.B) dst | Add Carry to dst |
ADDC(.B) #0,dst | * | * | * | * |
BR dst | Branch indirectly dst |
MOV dst,PC | – | – | – | – |
CLR(.B) dst | Clear dst |
MOV(.B) #0,dst | – | – | – | – |
CLRC | Clear Carry bit |
BIC #1,SR | – | – | – | 0 |
CLRN | Clear Negative bit |
BIC #4,SR | – | 0 | – | – |
CLRZ | Clear Zero bit |
BIC #2,SR | – | – | 0 | – |
DADC(.B) dst | Add Carry to dst decimally |
DADD(.B) #0,dst | * | * | * | * |
DEC(.B) dst | Decrement dst by 1 |
SUB(.B) #1,dst | * | * | * | * |
DECD(.B) dst | Decrement dst by 2 |
SUB(.B) #2,dst | * | * | * | * |
DINT | Disable interrupt |
BIC #8,SR | – | – | – | – |
EINT | Enable interrupt |
BIS #8,SR | – | – | – | – |
INC(.B) dst | Increment dst by 1 |
ADD(.B) #1,dst | * | * | * | * |
INCD(.B) dst | Increment dst by 2 |
ADD(.B) #2,dst | * | * | * | * |
INV(.B) dst | Invert dst |
XOR(.B) #–1,dst | * | * | * | * |
NOP | No operation |
MOV R3,R3 | – | – | – | – |
POP dst | Pop operand from stack |
MOV @SP+,dst | – | – | – | – |
RET | Return from subroutine |
MOV @SP+,PC | – | – | – | – |
RLA(.B) dst | Shift left dst arithmetically |
ADD(.B) dst,dst | * | * | * | * |
RLC(.B) dst | Shift left dst logically through Carry |
ADDC(.B) dst,dst | * | * | * | * |
SBC(.B) dst | Subtract Carry from dst |
SUBC(.B) #0,dst | * | * | * | * |
SETC | Set Carry bit |
BIS #1,SR | – | – | – | 1 |
SETN | Set Negative bit |
BIS #4,SR | – | 1 | – | – |
SETZ | Set Zero bit |
BIS #2,SR | – | – | 1 | – |
TST(.B) dst | Test dst (compare with 0) |
CMP(.B) #0,dst | 0 | * | * | 1 |