SLAU144 User guide

SLAU144K December 2004 – August 2022 MSP430AFE221 , MSP430AFE222 , MSP430AFE223 , MSP430AFE231 , MSP430AFE232 , MSP430AFE233 , MSP430AFE251 , MSP430AFE252 , MSP430AFE253 , MSP430F2001 , MSP430F2002 , MSP430F2003 , MSP430F2011 , MSP430F2012 , MSP430F2013 , MSP430F2101 , MSP430F2111 , MSP430F2112 , MSP430F2121 , MSP430F2122 , MSP430F2131 , MSP430F2132 , MSP430F2132-EP , MSP430F2232 , MSP430F2234 , MSP430F2252 , MSP430F2252-Q1 , MSP430F2254 , MSP430F2272 , MSP430F2272-Q1 , MSP430F2274 , MSP430F2274-EP , MSP430F233 , MSP430F2330 , MSP430F235 , MSP430F2350 , MSP430F2370 , MSP430F2410 , MSP430F2416 , MSP430F2417 , MSP430F2418 , MSP430F2419 , MSP430F247 , MSP430F2471 , MSP430F248 , MSP430F2481 , MSP430F249 , MSP430F2491 , MSP430F2616 , MSP430F2617 , MSP430F2618 , MSP430F2619 , MSP430G2001 , MSP430G2101 , MSP430G2102 , MSP430G2111 , MSP430G2112 , MSP430G2121 , MSP430G2131 , MSP430G2132 , MSP430G2152 , MSP430G2153 , MSP430G2201 , MSP430G2201-Q1 , MSP430G2202 , MSP430G2203 , MSP430G2210 , MSP430G2211 , MSP430G2212 , MSP430G2213 , MSP430G2221 , MSP430G2230 , MSP430G2231 , MSP430G2231-Q1 , MSP430G2232 , MSP430G2233 , MSP430G2252 , MSP430G2253 , MSP430G2302 , MSP430G2303 , MSP430G2312 , MSP430G2313 , MSP430G2332 , MSP430G2333 , MSP430G2352 , MSP430G2353 , MSP430G2402 , MSP430G2403 , MSP430G2412 , MSP430G2413 , MSP430G2432 , MSP430G2433 , MSP430G2444 , MSP430G2452 , MSP430G2453 , MSP430G2513 , MSP430G2533 , MSP430G2544 , MSP430G2553 , MSP430G2744 , MSP430G2755 , MSP430G2855 , MSP430G2955 , MSP430TCH5E

5.3 Basic Clock Module+ Registers

Table 5-1 lists the memory-mapped registers for the Basic Clock Module+.

Table 5-1 Basic Clock Module+ Registers

Address	Acronym	Register Name	Type	Reset	Section
56h	DCOCTL	DCO control	Read/write	60h with PUC	Section 5.4.1
57h	BCSCTL1	Basic clock system control 1	Read/write	87h with POR#SLAU144CLK1849	Section 5.4.2
58h	BCSCTL2	Basic clock system control 2	Read/write	00h with PUC	Section 5.4.3
53h	BCSCTL3	Basic clock system control 3	Read/write	05h with PUC#SLAU144CLK2213	Section 5.4.4
00h	IE1	SFR interrupt enable 1	Read/write	00h with PUC	Section 5.4.5
02h	IFG1	SFR interrupt flag 1	Read/write	02h with PUC	Section 5.4.6

(1) Some of the register bits are POR initialzed, and some are PUC initialized (see Section 5.4.2).

(2) The initial state of BCSCTL3 is 000h in the MSP430AFE2xx devices.

5.4.1 DCOCTL Register

DCO Control Register

DCOCTL is shown in Figure 5-10 and described in Table 5-2.

Return to Table 5-1.

Figure 5-10 DCOCTL Register

7	6	5	4	3	2	1	0
DCOx			MODx
rw-0	rw-1	rw-1	rw-0	rw-0	rw-0	rw-0	rw-0

Table 5-2 DCOCTL Register Field Descriptions

Bit	Field	Type	Reset	Description
7-5	DCOx	R/W	3h	DCO frequency select. These bits select which of the eight discrete DCO frequencies within the range defined by the RSELx setting is selected.
4-0	MODx	R/W	0h	Modulator selection. These bits define how often the f_DCO+1 frequency is used within a period of 32 DCOCLK cycles. During the remaining clock cycles (32 – MOD) the f_DCO frequency is used. Not useable when DCOx = 7.

5.4.2 BCSCTL1 Register

Basic Clock System Control 1 Register

BCSCTL1 is shown in Figure 5-11 and described in Table 5-3.

Return to Table 5-1.

Figure 5-11 BCSCTL1 Register

7	6	5	4	3	2	1	0
XT2OFF	XTS	DIVAx		RSELx
rw-(1)	rw-(0)	rw-(0)	rw-(0)	rw-0	rw-1	rw-1	rw-1

Table 5-3 BCSCTL1 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	XT2OFF	R/W	1h	XT2 off. This bit turns off the XT2 oscillator. 0b = XT2 is on 1b = XT2 is off if it is not used for MCLK or SMCLK.
6	XTS#SLAU144CLK3640 #SLAU144CLK8935	R/W	0h	LFXT1 mode select 0b = Low-frequency mode 1b = High-frequency mode
5-4	DIVAx	R/W	0h	Divider for ACLK 00b = /1 01b = /2 10b = /4 11b = /8
3-0	RSELx	R/W	7h	Range select. Sixteen different frequency ranges are available. The lowest frequency range is selected by setting RSELx = 0. RSEL3 is ignored when DCOR = 1.

(1) XTS = 1 is not supported in MSP430x20xx and MSP430G2xx devices (see GUID-2AABD3D2-3F65-456E-B44A-42650F15B33C.html#SLAU144CLK2256 and GUID-2AABD3D2-3F65-456E-B44A-42650F15B33C.html#SLAU144CLK8126 for details on supported settings for all devices).

(2) This bit is reserved in the MSP430AFE2xx devices.

5.4.3 BCSCTL2 Register

Basic Clock System Control 2 Register

BCSCTL2 is shown in Figure 5-12 and described in Table 5-4.

Return to Table 5-1.

Figure 5-12 BCSCTL2 Register

7	6	5	4	3	2	1	0
SELMx		DIVMx		SELS	DIVSx		DCOR
rw-0	rw-0	rw-0	rw-0	rw-0	rw-0	rw-0	rw-0

Table 5-4 BCSCTL2 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-6	SELMx	R/W	0h	Select MCLK. These bits select the MCLK source. 00b = DCOCLK 01b = DCOCLK 10b = XT2CLK when XT2 oscillator present on-chip. LFXT1CLK or VLOCLK when XT2 oscillator not present on-chip. 11b = LFXT1CLK or VLOCLK
5-4	DIVMx	R/W	0h	Divider for MCLK 00b = /1 01b = /2 10b = /4 11b = /8
3	SELS	R/W	0h	Select SMCLK. This bit selects the SMCLK source. 0b = DCOCLK 1b = XT2CLK when XT2 oscillator present. LFXT1CLK or VLOCLK when XT2 oscillator not present
2-1	DIVSx	R/W	0h	Divider for SMCLK 00b = /1 01b = /2 10b = /4 11b = /8
0	DCOR#SLAU144CLK6 #SLAU144CLK89352	R/W	0h	DCO resistor select. Not available in all devices. See the device-specific data sheet. 0b = Internal resistor 1b = External resistor

(1) Does not apply to MSP430x20xx or MSP430x21xx devices.

(2) This bit is reserved in the MSP430AFE2xx devices.

5.4.4 BCSCTL3 Register

Basic Clock System Control 3 Register

BCSCTL3 is shown in Figure 5-13 and described in Table 5-5.

Return to Table 5-1.

Figure 5-13 BCSCTL3 Register

7	6	5	4	3	2	1	0
XT2Sx		LFXT1Sx		XCAPx		XT2OF	LFXT1OF
rw-0	rw-0	rw-0	rw-0	rw-0	rw-1	r-0	r-(1)

Table 5-5 BCSCTL3 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-6	XT2Sx	R/W	0h	XT2 range select. These bits select the frequency range for XT2. 00b = 0.4- to 1-MHz crystal or resonator 01b = 1- to 3-MHz crystal or resonator 10b = 3- to 16-MHz crystal or resonator 11b = Digital external 0.4- to 16-MHz clock source
5-4	LFXT1Sx#SLAU144BCM1507	R/W	0h	Low-frequency clock select and LFXT1 range select. These bits select between LFXT1 and VLO when XTS = 0, and select the frequency range for LFXT1 when XTS = 1. MSP430G22x0: The LFXT1Sx bits should be programmed to 10b during the initialization and start-up code to select VLOCLK (for more details refer to Digital I/O chapter). The other bits are reserved and should not be altered. When XTS = 0: 00b = 32768-Hz crystal on LFXT1 01b = Reserved 10b = VLOCLK (Reserved in MSP430F21x1 devices) 11b = Digital external clock source When XTS = 1 (Not applicable for MSP430F20xx, MSP430G2xx1, MSP430G2xx2, MSP430G2xx3): 00b = 0.4- to 1-MHz crystal or resonator 01b = 1- to 3-MHz crystal or resonator 10b = 3- to 16-MHz crystal or resonator 11b = Digital external 0.4- to 16-MHz clock source LFXT1Sx definition for MSP430AFE2xx devices: 00b = Reserved 01b = Reserved 10b = VLOCLK 11b = Reserved
3-2	XCAPx#SLAU144BCM3785	R/W	1h	Oscillator capacitor selection. These bits select the effective capacitance seen by the LFXT1 crystal when XTS = 0. If XTS = 1 or if LFXT1Sx = 11 XCAPx should be 00. This bit is reserved in the MSP430AFE2xx devices. 00b = Approximately 1 pF 01b = Approximately 6 pF 10b = Approximately 10 pF 11b = Approximately 12.5 pF
1	XT2OF#SLAU144BCM9624	R	0h	XT2 oscillator fault. Does not apply to MSP430x2xx, MSP430x21xx, or MSP430x22xx devices. 0b = No fault condition present 1b = Fault condition present
0	LFXT1OF#SLAU144BCM3785	R	1h	LFXT1 oscillator fault. This bit is reserved in the MSP430AFE2xx devices. 0b = No fault condition present 1b = Fault condition present

(1) MSP430G22x0: The LFXT1Sx bits should be programmed to 10b during the initialization and start-up code to select VLOCLK (for more details, refer to the Digital I/O chapter). The other bits are reserved and should not be altered.

(2) This bit is reserved in the MSP430AFE2xx devices.

(3) Does not apply to MSP430x2xx, MSP430x21xx, or MSP430x22xx devices.

5.4.5 IE1 Register

SFR Interrupt Enable 1 Register

IE1 is shown in Figure 5-14 and described in Table 5-6.

Return to Table 5-1.

Figure 5-14 IE1 Register

7	6	5	4	3	2	1	0
						OFIE
						rw-0

Table 5-6 IE1 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-2				These bits may be used by other modules. See device-specific data sheet.
1	OFIE#SLAU144BCM8	R/W	0h	Oscillator fault interrupt enable. This bit enables the OFIFG interrupt. Because other bits in IE1 may be used for other modules, it is recommended to set or clear this bit using BIS.B or BIC.B instructions, rather than MOV.B or CLR.B instructions. MSP430G22x0: This bit should not be set. 0b = Interrupt not enabled 1b = Interrupt enabled
0				This bit may be used by other modules. See device-specific data sheet.

Bit

Field

Type

Reset

Description

7-2

These bits may be used by other modules. See device-specific data sheet.

OFIE#SLAU144BCM8

R/W

Oscillator fault interrupt enable. This bit enables the OFIFG interrupt. Because other bits in IE1 may be used for other modules, it is recommended to set or clear this bit using BIS.B or BIC.B instructions, rather than MOV.B or CLR.B instructions.

MSP430G22x0: This bit should not be set.

0b = Interrupt not enabled

1b = Interrupt enabled

This bit may be used by other modules. See device-specific data sheet.

(1) MSP430G22x0: This bit should not be set.

5.4.6 IFG1 Register

SFR Interrupt Flag 1 Register

IFG1 is shown in Figure 5-15 and described in Table 5-7.

Return to Table 5-1.

Figure 5-15 IFG1 Register

7	6	5	4	3	2	1	0
						OFIFG
						rw-1

Table 5-7 IFG1 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-2				These bits may be used by other modules. See device-specific data sheet.
1	OFIFG#SLAU144BCM4135	R/W	1h	Oscillator fault interrupt flag. Because other bits in IFG1 may be used for other modules, it is recommended to set or clear this bit using BIS.B or BIC.B instructions, rather than MOV.B or CLR.B instructions. 0b = Interrupt not pending 1b = Interrupt pending
0				This bit may be used by other modules. See device-specific data sheet.

Bit

Field

Type

Reset

Description

7-2

These bits may be used by other modules. See device-specific data sheet.

OFIFG#SLAU144BCM4135

R/W

Oscillator fault interrupt flag. Because other bits in IFG1 may be used for other modules, it is recommended to set or clear this bit using BIS.B or BIC.B instructions, rather than MOV.B or CLR.B instructions.

0b = Interrupt not pending

1b = Interrupt pending

This bit may be used by other modules. See device-specific data sheet.

(1) MSP430G22x0: The LFXT1 oscillator pins are not available in this device. The oscillator fault flag will always be set by hardware. The interrupt enable bit should not be set.