SLAU472C February   2013  – November 2023 TAS2505 , TAS2505-Q1

 

  1.   1
  2.   Trademarks
  3. 1 TAS2505 Device Overview
  4. 2Description
    1. 2.1 Typical Circuit Configuration
    2. 2.2 Circuit Configuration with Internal LDO
  5. 3 TAS2505 Application
    1. 3.1 Terminal Descriptions
      1. 3.1.1 Digital Pins
      2. 3.1.2 Analog Pins
      3. 3.1.3 Multifunction Pins
      4. 3.1.4 Register Settings for Multifunction Pins
    2. 3.2 Audio Analog I/O
    3. 3.3 Analog Signals
      1. 3.3.1 Analog Inputs AINL and AINR
    4. 3.4 Audio DAC and Audio Analog Outputs
      1. 3.4.1  DAC
        1. 3.4.1.1 DAC Processing Blocks
        2. 3.4.1.2 DAC Processing Blocks – Signal Chain Details
          1. 3.4.1.2.1 Three Biquads, Filter A
          2. 3.4.1.2.2 Six Biquads, First-Order IIR, Filter A or B
        3. 3.4.1.3 DAC User-Programmable Filters
          1. 3.4.1.3.1 First-Order IIR Section
          2. 3.4.1.3.2 Biquad Section
        4. 3.4.1.4 DAC Interpolation Filter Characteristics
          1. 3.4.1.4.1 Interpolation Filter A
          2. 3.4.1.4.2 Interpolation Filter B
      2. 3.4.2  DAC Gain Setting
        1. 3.4.2.1 PowerTune Modes
        2. 3.4.2.2 DAC Digital-Volume Control
      3. 3.4.3  Interrupts
      4. 3.4.4  Programming DAC Digital Filter Coefficients
      5. 3.4.5  Updating DAC Digital Filter Coefficients During PLAY
      6. 3.4.6  Digital Mixing and Routing
      7. 3.4.7  Analog Audio Routing
        1. 3.4.7.1 Analog Output Volume Control
        2. 3.4.7.2 Headphone Analog Output Volume Control
        3. 3.4.7.3 Class-D Speaker Analog Output Volume Control
      8. 3.4.8  Analog Outputs
        1. 3.4.8.1 Headphone Drivers
        2. 3.4.8.2 Speaker Driver
      9. 3.4.9  Audio Output-Stage Power Configurations
      10. 3.4.10 5V LDO
      11. 3.4.11 POR
      12. 3.4.12 DAC Setup
    5. 3.5 PowerTune
      1. 3.5.1 PowerTune Modes
        1. 3.5.1.1 DAC - Programming PTM_P1 to PTM_P4
        2. 3.5.1.2 Processing Blocks
      2. 3.5.2 DAC Power Consumption
        1. 3.5.2.1 DAC, Mono, 48 kHz, Highest Performance, DVDD = IOVDD = 1.8 V, AVDD = 1.8 V, SPKVDD = 3.6V
        2. 3.5.2.2 DAC, Mono, Lowest Power Consumption
        3. 3.5.2.3 DAC, Mono, 8 kHz, Highest Performance, DVDD = IOVDD = 1.8 V, AVDD = 1.8 V, SPKVDD = 3.6 V
        4. 3.5.2.4 DAC, Mono, Lowest Power Consumption
      3. 3.5.3 Speaker output Power Consumption
        1. 3.5.3.1 Speaker output, Mono, 48 kHz, Highest Performance, DVDD = IOVDD = 1.8 V, AVDD = 1.8 V, SPKVDD = 3.6V
        2. 3.5.3.2 Speaker output, Mono, Lowest Power Consumption
        3. 3.5.3.3 Speaker output, Mono, 8 kHz, Highest Performance, DVDD = IOVDD = 1.8 V, AVDD = 1.8 V, SPKVDD = 3.6V
        4. 3.5.3.4 Speaker output, Mono, Lowest Power Consumption
      4. 3.5.4 Headphone output Power Consumption
        1. 3.5.4.1 Headphone output, Mono, 48 kHz, Highest Performance, DVDD = IOVDD = 1.8 V, AVDD = 1.8 V, SPKVDD = 3.6V
        2. 3.5.4.2 Headphone output, Mono, Lowest Power Consumption, DVDD = IOVDD = 1.8 V, AVDD = 1.5 V, SPKVDD = 3.6V
        3. 3.5.4.3 Headphone output, Mono, 8 kHz, Highest Performance, DVDD = IOVDD = 1.8 V, AVDD = 1.8 V, SPKVDD = 3.6V
        4. 3.5.4.4 Headphone output, Mono, Lowest Power Consumption, DVDD = IOVDD = 1.8 V, AVDD = 1.8 V, SPKVDD = 3.6V
    6. 3.6 CLOCK Generation and PLL
      1. 3.6.1 PLL
        1. 3.6.1.1 PLL Description
    7. 3.7 Digital Audio and Control Interface
      1. 3.7.1 Digital Audio Interface
        1. 3.7.1.1 Right-Justified Mode
        2. 3.7.1.2 Left-Justified Mode
        3. 3.7.1.3 I2S Mode
        4. 3.7.1.4 DSP Mode
        5. 3.7.1.5 Primary and Secondary Digital Audio Interface Selection
      2. 3.7.2 Control Interface
        1. 3.7.2.1 I2C Control Mode
        2. 3.7.2.2 SPI Digital Interface
    8. 3.8 Power Supply
      1. 3.8.1 System Level Considerations
        1. 3.8.1.1 All Supplies from Single Voltage Rail with using the internal LDO (2.75V to 5.5V)
          1. 3.8.1.1.1 Standby Mode
          2. 3.8.1.1.2 Shutdown Mode
        2. 3.8.1.2 Supply from Dual Voltage Rails (2.75V to 5.5V and 1.8V)
          1. 3.8.1.2.1 Standby Mode
          2. 3.8.1.2.2 Shutdown Mode
        3. 3.8.1.3 Other Supply Options
    9. 3.9 Device Special Functions
      1. 3.9.1 Interrupts
  6. 4Device Initialization
    1. 4.1 Power On Sequence
      1. 4.1.1 Power On Sequence 1 – Separate Digital and Analog Supplies
      2. 4.1.2 Power On Sequence 2 – Shared 1.8 V Analog Supply to DVDD
    2. 4.2 Device Initialization
      1. 4.2.1 Reset by RST pin and POR
      2. 4.2.2 Device Start-Up Lockout Times
      3. 4.2.3 PLL Start-Up
      4. 4.2.4 Power-Stage Reset
      5. 4.2.5 Software Power Down
      6. 4.2.6 Device Common Mode Voltage
  7. 5Example Setups
    1. 5.1 Example Register Setup to Play Digital Data Through DAC and Headphone/Speaker Outputs
    2. 5.2 Example Register Setup to Play Digital Data Through DAC and Headphone Output
    3. 5.3 Example Register Setup to Play AINL and AINR Through Headphone/Speaker Outputs
    4. 5.4 Example Register Setup to Play AINL and AINR Through Headphone Output
    5. 5.5 Example Register Setup to Play Digital Data Through DAC and Headphone/Speaker Outputs With 3 Programmable Biquads
    6. 5.6 Example Register Setup to Play Digital Data Through DAC and Headphone/Speaker Outputs With 6 Programmable Biquads
  8. 6Register Map
    1. 6.1 TAS2505 Register Map
      1. 6.1.1  Control Registers, Page 0 (Default Page): Clock Multipliers, Dividers, Serial Interfaces, Flags, Interrupts, and GPIOs
      2. 6.1.2  Control Registers, Page 1: DAC Routing, Power-Controls and MISC Logic Related Programmabilities
      3. 6.1.3  Page 2 - 43: Reserved Register
      4. 6.1.4  Page 44: DAC Programmable Coefficients RAM
      5. 6.1.5  Page 45 - 52: DAC Programmable Coefficients RAM
      6. 6.1.6  Page 53 - 61: Reserved Register
      7. 6.1.7  Page 62 - 70: DAC Programmable Coefficients RAM
      8. 6.1.8  Pages 71 – 255: Reserved Register
      9. 6.1.9  DAC Coefficients A+B
      10. 6.1.10 DAC Defaults
  9. 7Revision History

6.1.1 Control Registers, Page 0 (Default Page): Clock Multipliers, Dividers, Serial Interfaces, Flags, Interrupts, and GPIOs

Page 0 / Register 0: Page Select Register - 0x00 / 0x00
BITRead/WriteReset ValueDESCRIPTION
D7–D0R/W0000 00000-255: Selects the Register Page for next read or write command. See the Table "Summary of Memory Map" for details.
Page 0 / Register 1: Software Reset Register - 0x00 / 0x01
BITRead/WriteReset ValueDESCRIPTION
D7–D1R0000 000Reserved. Write only zeros to these bits.
D0W0Self clearing software reset bit
0: Don't care
1: Self-clearing software reset
Page 0 / Register 2: Reserved Register - 0x00 / 0x02
BITRead/WriteReset ValueDESCRIPTION
D7-D0R0XXX 0XXXReserved. Do not write to this register. (Read Only)
Page 0 / Register 3: Reserved Register - 0x00 / 0x03
BITRead/WriteReset ValueDESCRIPTION
D7–D0R/W0000 0000Reserved. Write only zeros to these bits.
Page 0 / Register 4: Clock Setting Register 1, Multiplexers - 0x00 / 0x04
BITRead/WriteReset ValueDESCRIPTION
D7R0Reserved. Write only the default value.
D6R/W0Select PLL Range
0: Low PLL Clock Range
1: High PLL Clock Range
D5-D4R00Reserved. Write only the default values.
D3-D2R/W00Select PLL Input Clock
00: MCLK pin is input to PLL
01: BCLK pin is input to PLL
10: GPIO pin is input to PLL
11: DIN pin is input to PLL
D1-D0R/W00Select CODEC_CLKIN
00: MCLK pin is CODEC_CLKIN
01: BCLK pin is CODEC_CLKIN
10: GPIO pin is CODEC_CLKIN
11: PLL Clock is CODEC_CLKIN
Page 0 / Register 5: Clock Setting Register 2, PLL P and R Values - 0x00 / 0x05
BITRead/WriteReset ValueDESCRIPTION
D7R/W00: PLL is powered down.
1: PLL is powered up.
D6–D4R/W001000: PLL divider P = 8
001: PLL divider P = 1
010: PLL divider P = 2
...
110: PLL divider P = 6
111: PLL divider P = 7
D3–D0R/W00010000: Reserved. Do not use
0001: PLL multiplier R = 1
0010: PLL multiplier R = 2
0011: PLL multiplier R = 3
0100: PLL multiplier R = 4
...
0101…0111: Reserved. Do not use
Page 0 / Register 6: Clock Setting Register 3, PLL J Values - 0x00 / 0x06
BITRead/WriteReset ValueDESCRIPTION
D7–D6R00Reserved. Write only the default values.
D5–D0R/W00 0100PLL divider J value
00 0000…00 0011: Do not use
00 0100: J = 4
00 0101: J = 5
…
11 1110: J = 62
11 1111: J = 63
Page 0 / Register 7: Clock Setting Register 4, PLL D Values (MSB) - 0x00 / 0x07
BITRead/WriteReset ValueDESCRIPTION
D7–D6R00Reserved. Write only default values.
D5–D0R/W00 0000PLL divider D value (MSB)
PLL divider D value(MSB) and PLL divider D value(LSB)
00 0000 0000 0000: D=0000
00 0000 0000 0001: D=0001
…
10 0111 0000 1110: D=9998
10 0111 0000 1111: D=9999
10 0111 0001 0000…11 1111 1111 1111: Do not use
Note: This register will be updated only when the Page-0, Reg-8 is written immediately after Page-0, Reg-7.
Page 0 / Register 8: Clock Setting Register 5, PLL D Values (LSB) - 0x00 / 0x08
BITRead/WriteReset ValueDESCRIPTION
D7–D0R/W0000 0000PLL divider D value (LSB)
PLL divider D value(MSB) and PLL divider D value(LSB)
00 0000 0000 0000: D=0000
00 0000 0000 0001: D=0001
…
10 0111 0000 1110: D=9998
10 0111 0000 1111: D=9999
10 0111 0001 0000…11 1111 1111 1111: Do not use
Note: Page-0, Reg-8 should be written immediately after Page-0, Reg-7.
Page 0 / Registers 9–10: Reserved - 0x00 / 0x09-0x0A
BITRead/WriteReset ValueDESCRIPTION
D7–D0R/W0000 0000Reserved. Write only the default values.
Page 0 / Register 11: Clock Setting Register 6, NDAC Values - 0x00 / 0x0B
BITRead/WriteReset ValueDESCRIPTION
D7R/W0NDAC Divider Power Control
0: NDAC divider powered down
1: NDAC divider powered up
D6–D0R/W000 0001NDAC Value
000 0000: NDAC=128
000 0001: NDAC=1
000 0010: NDAC=2
…
111 1110: NDAC=126
111 1111: NDAC=127
Note: Please check the clock frequency requirements in the Overview section.
Page 0 / Register 12: Clock Setting Register 7, MDAC Values - 0x00 / 0x0C
BITRead/WriteReset ValueDESCRIPTION
D7R/W0MDAC Divider Power Control
0: MDAC divider powered down
1: MDAC divider powered up
D6–D0R/W000 0001MDAC Value
000 0000: MDAC=128
000 0001: MDAC=1
000 0010: MDAC=2
…
111 1110: MDAC=126
111 1111: MDAC=127
Note: Please check the clock frequency requirements in the Overview section.
Page 0 / Register 13: DAC OSR Setting Register 1, MSB Value - 0x00 / 0x0D
BITRead/WriteReset ValueDESCRIPTION
D7–D2R0000 00Reserved. Write only the default values.
D1–D0R/W00DAC OSR (DOSR) MSB Setting
DAC OSR(MSB) and DAC OSR (LSB)
00 0000 0000: DOSR=1024
00 0000 0001: DOSR=1
00 0000 0010: DOSR=2
…
11 1111 1110: DOSR=1022
11 1111 1111: DOSR=1023
Note: This register is updated when Page-0, Reg-14 is written to immediately after Page-0, Reg-13.
Page 0 / Register 14: DAC OSR Setting Register 2, LSB Value - 0x00 / 0x0E
BITRead/WriteReset ValueDESCRIPTION
D7–D0R/W1000 0000DAC OSR (DOSR) LSB Setting
DAC OSR(MSB) and DAC OSR (LSB)
00 0000 0000: DOSR=1024
00 0000 0001: DOSR=1
00 0000 0010: DOSR=2
…
11 1111 1110: DOSR=1022
11 1111 1111: DOSR=1023
Note: This register should be written immediately after Page-0, Reg-13.
Page 0 / Register 15: Reserved Register - 0x00 / 0x0F
BITRead/WriteReset ValueDESCRIPTION
D7R0000 0010Reserved. Write only the default values.
Page 0 / Registers 16 - 24: Reserved Register - 0x00 / 0x10 - 0x12
BITRead/WriteReset ValueDESCRIPTION
D7–D0R0000 0000Reserved. Write only the default value.
Page 0 / Registers 25: Clock Setting Register 10, Multiplexers - 0x00 / 0x19
BITRead/WriteReset ValueDESCRIPTION
D7–D3R0000 0Reserved. Write only the default values.
D2–D0R/W000CDIV_CLKIN Clock Selection
000: CDIV_CLKIN = MCLK
001: CDIV_CLKIN = BCLK
010: CDIV_CLKIN = DIN
011: CDIV_CLKIN = PLL_CLK
100: CDIV_CLKIN = DAC_CLK
101: CDIV_CLKIN = DAC_MOD_CLK
Page 0 / Registers 26: Clock Setting Register 11, CLKOUT M divider value - 0x00 / 0x1A
BITRead/WriteReset ValueDESCRIPTION
D7R/W0CLKOUT M divider power control
0: CLKOUT M divider is powered down.
1: CLKOUT M divider is powered up.
D6–D0R/W000 0001CLKOUT M divider value
000 0000: CLKOUT divider M = 128
000 0001: CLKOUT divider M = 1
000 0010: CLKOUT divider M = 2
...
111 1110: CLKOUT divider M = 126
111 1111: CLKOUT divider M = 127
Note: Check the clock frequency requirements in the application overview section.
Page 0 / Register 27: Audio Interface Setting Register 1 - 0x00 / 0x1B
BITRead/WriteReset ValueDESCRIPTION
D7–D6R/W00Audio Interface Selection
00: Audio Interface = I2S
01: Audio Interface = DSP
10: Audio Interface = RJF
11: Audio Interface = LJF
D5–D4R/W00Audio Data Word length
00: Data Word length = 16 bits
01: Data Word length = 20 bits
10: Data Word length = 24 bits
11: Data Word length = 32 bits
D3R/W0BCLK Direction Control
0: BCLK is input to the device
1: BCLK is output from the device
D2R/W0WCLK Direction Control
0: WCLK is input to the device
1: WCLK is output from the device
D1R0Reserved. Write only default value.
D0R0Reserved. Write only default value.
Page 0 / Register 28: Audio Interface Setting Register 2, Data offset setting - 0x00 / 0x1C
BITRead/WriteReset ValueDESCRIPTION
D7–D0R/W0000 0000Data Offset Value
0000 0000: Data Offset = 0 BCLK's
0000 0001: Data Offset = 1 BCLK's
…
1111 1110: Data Offset = 254 BCLK's
1111 1111: Data Offset = 255 BCLK's
Page 0 / Register 29: Audio Interface Setting Register 3 - 0x00 / 0x1D
BITRead/WriteReset ValueDESCRIPTION
D7–D6R/W00Reserved. Write only default values.
D5R/W0Reserved. Write only default value.
D4R/W0Reserved. Write only default values.
D3R/W0Audio Bit Clock Polarity Control
0: Default Bit Clock polarity
1: Bit Clock is inverted w.r.t. default polarity
D2R/W0Primary BCLK and Primary WCLK Power control
0: Primary BCLK and Primary WCLK buffers are powered up when they are used in clock generation even when the codec is powered down
1: Priamry BCLK and Primary WCLK buffers are powered down when the codec is powered down
D1–D0R/W00BDIV_CLKIN Multiplexer Control
00: BDIV_CLKIN = DAC_CLK
01: BDIV_CLKIN = DAC_MOD_CLK
10: Do not use
11: Do not use
Page 0 / Register 30: Clock Setting Register 12, BCLK N Divider- 0x00 / 0x1E
BITRead/WriteReset ValueDESCRIPTION
D7R/W0BCLK N Divider Power Control
0: BCLK N-divider is powered down.
1: BCLK N-divider is powered up.
D6–D0R/W000 0001BCLK N Divider value
000 0000: BCLK divider N = 128
000 0001: BCLK divider N = 1
...
111 1110: BCLK divider N = 126
111 1111: BCLK divider N = 127
Page 0 / Register 31: Audio Interface Setting Register 4, Secondary Audio Interface - 0x00 / 0x1F
BITRead/WriteReset ValueDESCRIPTION
D7R0Reserved. Write only default values.
D6–D5R/W00Secondary Bit Clock Multiplexer
00: Secondary Bit Clock = GPIO
01: Secondary Bit Clock = SCLK
10: Secondary Bit Clock = MISO
11: Secondary Bit Clock = DOUT
D4–D3R/W00Secondary Word Clock Multiplexer
00: Secondary Word Clock = GPIO
01: Secondary Word Clock = SCLK
10: Secondary Word Clock = MISO
11: Secondary Word Clock = DOUT
D2-D1R00Reserved. Write only default values.
D0R/W0Secondary Data Input Multiplexer
0: Secondary Data Input = GPIO
1: Secondary Data Input = SCLK
Page 0 / Register 32: Audio Interface Setting Register 5 - 0x00 / 0x20
BITRead/WriteReset ValueDESCRIPTION
D7–D4R0000Reserved. Write only default values.
D3R/W0Primary / Secondary Bit Clock Control
0: Primary Bit Clock(BCLK) is used for Audio Interface and Clocking
1: Secondary Bit Clock is used for Audio Interface and Clocking
D2R/W0Primary / Secondary Word Clock Control
0: Primary Word Clock(WCLK) is used for Audio Interface
1: Secondary Word Clock is used for Audio Interface
D1R0Reserved. Write only default values.
D0R/W0Audio Data In Control
0: DIN is used for Audio Data In
1: Secondary Data In is used for Audio Data In
Page 0 / Register 33: Audio Interface Setting Register 6 - 0x00 / 0x21
BITRead/WriteReset ValueDESCRIPTION
D7R/W0BCLK Output Control
0: BCLK Output = Generated Primary Bit Clock
1: BCLK Output = Secondary Bit Clock Input
D6R/W0Secondary Bit Clock Output Control
0: Secondary Bit Clock = BCLK input
1: Secondary Bit Clock = Generated Primary Bit Clock
D5–D4R/W00WCLK Output Control
00: WCLK Output = Generated DAC_FS
01: Reserved. Do not use.
10: WCLK Output = Secondary Word Clock Input
11: Reserved. Do not use
D3–D2R/W00Secondary Word Clock Output Control
00: Secondary Word Clock output = WCLK input
01: Secondary Word Clock output = Generated DAC_FS
10: Reserved. Do not use.
11: Reserved. Do not use
D1R/W0Primary Data Out output control
0: Reserved. Do not use.
1: DOUT output = Secondary Data Input (Loopback)
D0R/W0Secondary Data Out output control
0: Secondary Data Output = DIN input (Loopback)
1: Reserved. Do not use.
Page 0 / Register 34: Digital Interface Misc. Setting Register - 0x00 / 0x22
BITRead/WriteReset ValueDESCRIPTION
D7R0Reserved. Write only default value.
D6R0Reserved. Write only default value.
D5R/W0I2C General Call Address Configuration
0: I2C General Call Address will be ignored
1: I2C General Call Address accepted
D4-D0R0 0000Reserved. Write only default values.
Page 0 / Register 35 - 36 Reserved- 0x00 / 0x23 - 0x24
BITRead/WriteReset ValueDESCRIPTION
D7–D0R0000 0000Reserved. Write only zeros to these bits.
Page 0 / Register 37: DAC Flag Register 1 - 0x00 / 0x25
BITRead/WriteReset ValueDESCRIPTION
D7R0DAC Power Status Flag
0: DAC powered down
1: DAC powered up
D6R0Reserved. Write only zeros to these bits.
D5R0Headphone Driver (HPOUT) Power Status Flag
0: HPOUT driver powered down
1: HPOUT driver powered up
D4-D0R0 0000Reserved. Write only zeros to these bits.
Page 0 / Register 38: DAC Flag Register 2- 0x00 / 0x26
BITRead/WriteReset ValueDESCRIPTION
D7–D5R000Reserved. Write only zeros to these bits.
D4R0DAC PGA Status Flag
0: Gain applied in DAC PGA is not equal to Gain programmed in Control Register
1: Gain applied in DAC PGA is equal to Gain programmed in Control Register"
D3–D0R0000Reserved. Write only zeros to these bits.
Page 0 / Register 39 - 41: Reserved - 0x00 / 0x27-0x29
BITRead/WriteReset ValueDESCRIPTION
D7-D0R0000 0000Reserved. Write only default values.
Page 0 / Registers 42: Sticky Flag Register 1- 0x00 / 0x2A
BITRead/WriteReset ValueDESCRIPTION
D7R0DAC Overflow Status. This sticky flag will self clear on read
0: No overflow in DAC
1: Overflow has happened in DAC since last read of this register"
D6R0Reserved. Write only default value.
D5R0Reserved. Write only default value.
D4-D0R0Reserved. Write only default value.
Page 0 / Registers 43: Interrupt Flags Register 1 - 0x00 / 0x2B
BITRead/WriteReset ValueDESCRIPTION
D7R0DAC Overflow Status.
0: No overflow in DAC
1: Overflow condition is present in DAC at the time of reading the register"
D6R0Reserved. Write only default value.
D5R0Reverved. Write only default value.
D4-D0R0 0000Reserved. Write only default value.
Page 0 / Register 44: Sticky Flag Register 2 - 0x00 / 0x2C
BITRead/WriteReset ValueDESCRIPTION
D7R0HPOUT Over Current Detect Flag
0: Over Current not detected on HPOUT
1: Over Current detected on HPOUT (will be cleared when the register is read)"
D6-D4R000Reserved. Write only default values.
D3R0Reserved. Write only default value.
D2R0Reserved. Write only default value.
D1R0Reverved. Write only default value.
D0R0Reserved. Write only default value.
Page 0 / Register 45: Reserved - 0x00 / 0x2D
BITRead/WriteReset ValueDESCRIPTION
D7-D0R0000 0000Reserved. Write only default values.
Page 0 / Register 46: Interrupt Flag Register 2 - 0x00 / 0x2E
BITRead/WriteReset ValueDESCRIPTION
D7R0HPOUT Over Current Detect Flag
0: Over Current not detected on HPOUT
1: Over Current detected on HPOUT
D6-D4R0Reserved. Write only default value.
D3R0Reserved. Write only default value.
D2R0Reserved. Write only default value.
D1R0Reserved. Write only default value.
D0R0Reserved. Write only default value.
Page 0 / Register 47: Reserved - 0x00 / 0x2F
BITRead/WriteReset ValueDESCRIPTION
D7-D0R0000 0000Reserved. Write only default value.
Page 0 / Register 48: INT1 Control Register - 0x00 / 0x30
BITRead/WriteReset ValueDESCRIPTION
D7-D6R0Reserved. Write only default value.
D5R0Reserved. Write only default value.
D4R0Reserved. Write only default value.
D3R/W0INT1 Interrupt for Over Current Condition
0: Headphone Over Current condition will not generate a INT1 interrupt.
1: Headphone Over Current condition will generate a INT1 interrupt.
D2R0Reverved. Write only default value.
D1R0Reserved. Write only default value.
D0R/W0INT1 pulse control
0: INT1 is active high interrupt of 1 pulse of approx. 2ms duration
1: INT1 is active high interrupt of multiple pulses, each of duration 2ms. To stop the pulse train, read Page-0, Reg-42, or 44
Page 0 / Register 49: INT2 Interrupt Control Register - 0x00 / 0x31
BITRead/WriteReset ValueDESCRIPTION
D7-D6R0Reserved. Write only default value.
D5R0Reserved. Write only default value.
D4R0Reserved. Write only default value.
D3R/W0INT2 Interrupt for Over Current Condition
0: Headphone Over Current condition will not generate a INT2 interrupt.
1: Headphone Over Current condition will generate a INT2 interrupt.
D2R0Reserved. Write only default value.
D1R0Reserved. Write only default value.
D0R/W0INT2 pulse control
0: INT2 is active high interrupt of 1 pulse of approx. 2ms duration
1: INT2 is active high interrupt of multiple pulses, each of duration 2ms. To stop the pulse train, read Page-0, Reg-42, or 44
Page 0 / Register 50 and 51 Reserved - 0x00 / 0x32-0x33
BITRead/WriteReset ValueDESCRIPTION
D7-D0R/W0000 0000Reserved. Write only Reset Values.
Page 0 / Register 52: GPIO/DOUT Control Register - 0x00 / 0x34
BITRead/WriteReset ValueDESCRIPTION
D7–D6R00Reserved. Write only default values.
D5–D2R/W0000GPIO Control
0000: GPIO input/output disabled.
0001: GPIO input is used for secondary audio interface or clock input. Configure other registers to choose the functionality of GPIO input.
0010: GPIO is general purpose input
0011: GPIO is general purpose output
0100: GPIO output is CLKOUT
0101: GPIO output is INT1
0110: GPIO output is INT2
0111: GPIO output is 0
1000: GPIO output is secondary bit-clock for Audio Interface.
1001: GPIO output is secondary word-clock for Audio Interface.
1010: GPIO output is 0
1011-1101: Reserved. Do not use.
1110: GPIO output is DOUT for Audio Interface according to Register 53 programming.
1111: Reserved. Do not use.
D1RXGPIO Input Pin state, used along with GPIO as general purpose input
D0R/W0GPIO as general purpose output control
0: GPIO pin is driven to '0' in general purpose output mode
1: GPIO pin is driven to '1' in general purpose output mode
Page 0 / Register 53: DOUT Function Control Register - 0x00 / 0x35
BITRead/WriteReset ValueDESCRIPTION
D7–D5R000Reserved. Write only default values.
D4R/W1DOUT Bus Keeper Control
0: DOUT Bus Keeper Enabled
1: DOUT Bus Keeper Disabled
D3-D1R/W001DOUT MUX Control
000: DOUT disabled
001: DOUT disabled
010: DOUT is General Purpose Output
011: DOUT is CLKOUT
100: DOUT is INT1
101: DOUT is INT2
110: DOUT is Secondary BCLK
111: DOUT is Secondary WCLK
D0R/W0DOUT as General Purpose Output
0: DOUT General Purpose Output Value = 0
1: DOUT General Purpose Output Value = 1
Page 0 / Register 54: DIN Function Control Register - 0x00 / 0x36
BITRead/WriteReset ValueDESCRIPTION
D7–D3R0 0000Reserved. Write only reserved values.
D2–D1R/W01DIN function control
00: DIN pin is disabled
01: DIN is enabled for Primary Data Input or General Purpose Clock input
10: DIN is used as General Purpose Input
11: Reserved. Do not use
D0RXValue of DIN input pin. To be used when for General Purpose Input
Page 0 / Register 55: MISO Function Control Register - 0x00 / 0x37
BITRead/WriteReset ValueDESCRIPTION
D7–D5R000Reserved. Write only reserved values.
D4-D1R/W0001MISO function control
0000: MISO buffer disabled
0001: MISO is used for data output in SPI interface, is disabled for I2C interface
0010: MISO is General Purpose Output
0011: MISO is CLKOUT output
0100: MISO is INT1 output
0101: MISO is INT2 output
0110: Reserved
0111: Reserved
1000: MISO is Secondary Data Output for Audio Interface
1001: MISO is Secondary Bit Clock for Audio Interface
1010: MISO is Secondary Word Clock for Audio Interface
1011-1111: Reserved. Do not use
D0R/W0Value to be driven on MISO pin when used as General Purpose Output
0: MISO General Purpose Output Value = 0
1: MISO General Purpose Output Value = 1
Page 0 / Register 56: SCLK/DMDIN2 Function Control Register- 0x00 / 0x38
BITRead/WriteReset ValueDESCRIPTION
D7–D3R0 0000Reserved. Write only default values.
D2–D1R/W01SCLK function control
00: SCLK pin is disabled
01: SCLK pin is enabled for SPI clock in SPI Interface mode or when in I2C Interface enabled for Secondary Data Input or Secondary Bit Clock Input or Secondary Word Clock.
10: SCLK is enabled as General Purpose Input
11: Reserved. Do not use
D0RXValue of SCLK input pin when used as General Purpose Input
Page 0 / Register 57 - 59: Reserved - 0x00 / 0x39-0x3B
BITRead/WriteReset ValueDESCRIPTION
D7–D0R0000 0000Reserved. Write only default values.
Page 0 / Register 60: DAC Instruction Set - 0x00 / 0x3C
BITRead/WriteReset ValueDESCRIPTION
D7–D5R0Reserved. Write only default value.
D4–D0R/W0 00010 0000: Reverved
0 0001: DAC Signal Processing Block PRB_P1
0 0010: DAC Signal Processing Block PRB_P2
0 0011: DAC Signal Processing Block PRB_P3
0 0100-1 1111: Reserved. Do not use
Page 0 / Register 61-62: Reserved Registers - 0x00 / 0x3D - 0x3E
BITRead/WriteReset ValueDESCRIPTION
D7–D0R0000 0000Reserved. Write only default values.
Page 0 / Register 63: DAC Channel Setup Register 1 - 0x00 / 0x3F
BITRead/WriteReset ValueDESCRIPTION
D7R/W0DAC Channel Power Control
0: DAC Channel Powered Down
1: DAC Channel Powered Up
D6R0Reserved. Write only default value.
D5–D4R/W01DAC Data path Control
00: DAC data is disabled
01: DAC data is picked from Left Channel Audio Interface Data
10: DAC data is picked from Right Channel Audio Interface Data
11: DAC data is picked from Mono Mix of Left and Right Channel Audio Interface Data
D3–D2R01Reserved. Write only default values.
D1–D0R/W00DAC Channel Volume Control's Soft-Step control
00: Soft-Stepping is 1 step per 1 DAC Word Clock
01: Soft-Stepping is 1 step per 2 DAC Word Clocks
10: Soft-Stepping is disabled
11: Reserved. Do not use
Page 0 / Register 64: DAC Channel Setup Register 2 - 0x00 / 0x40
BITRead/WriteReset ValueDESCRIPTION
D7R0Reserved. Write only default value.
D6-D4R/W000DAC Auto Mute Control
000: Auto Mute disabled
001: DAC is auto muted if input data is DC for more than 100 consecutive inputs
010: DAC is auto muted if input data is DC for more than 200 consecutive inputs
011: DAC is auto muted if input data is DC for more than 400 consecutive inputs
100: DAC is auto muted if input data is DC for more than 800 consecutive inputs
101: DAC is auto muted if input data is DC for more than 1600 consecutive inputs
110: DAC is auto muted if input data is DC for more than 3200 consecutive inputs
111: DAC is auto muted if input data is DC for more than 6400 consecutive inputs
D3R/W1DAC Channel Mute Control
0: DAC Channel not muted
1: DAC Channel muted
D2R/W1Reserved. Write only default value.
D1-D0R/W00Reserved. Write only default values.
Page 0 / Register 65: DAC Channel Digital Volume Control Register - 0x00 / 0x41
BITRead/WriteReset ValueDESCRIPTION
D7–D0R/W0000 0000DAC Channel Digital Volume Control Setting
0111 1111-0011 0001: Reserved. Do not use
0011 0000: Digital Volume Control = +24dB
0010 1111: Digital Volume Control = +23.5dB
…
0000 0001: Digital Volume Control = +0.5dB
0000 0000: Digital Volume Control = 0.0dB
1111 1111: Digital Volume Control = -0.5dB
...
1000 0010: Digital Volume Control = -63dB
1000 0001: Digital Volume Control = -63.5dB
1000 0000: Reserved. Do not use"
Page 0 / Register 66-74: Reserved Register - 0x00 / 0x42 -0x4A
BITRead/WriteReset ValueDESCRIPTION
D7–D0R0000 0000Reserved. Write only default values.
Page 0 / Register 75: Reserved Register - 0x00 / 0x4B
BITRead/WriteReset ValueDESCRIPTION
D7–D0R1110 1110Reserved. Write only default values.
Page 0 / Register 76: Reserved Register - 0x00 / 0x4C
BITRead/WriteReset ValueDESCRIPTION
D7–D0R0001 0000Reserved. Write only default values.
Page 0 / Register 77: Reserved Register - 0x00 / 0x4D
BITRead/WriteReset ValueDESCRIPTION
D7–D0R1101 1000Reserved. Write only default values.
Page 0 / Register 78: Reserved Register - 0x00 / 0x4E
BITRead/WriteReset ValueDESCRIPTION
D7–D0R0111 1110Reserved. Write only default values.
Page 0 / Register 79: Reserved Register - 0x00 / 0x4F
BITRead/WriteReset ValueDESCRIPTION
D7–D0R1110 0011Reserved. Write only default values.
Page 0 / Register 80-81: Reserved register - 0x00 / 0x50 -0x51
BITRead/WriteReset ValueDESCRIPTION
D7–D0R0000 0000Reserved. Write only default values.
Page 0 / Register 82 - 127 Reserved Registers - 0x00 / 0x520x7F
BITRead/WriteReset ValueDESCRIPTION
D7–D0R0000 0000Reserved. Write only default values.