SLAU640B April   2019  – March 2023 ADC12DJ5200SE

 

  1.   Introduction
  2. 1Trademarks
  3. 2Equipment
    1. 2.1 Evaluation Board Feature Identification Summary
    2. 2.2 Required Equipment
  4. 3Setup Procedure
    1. 3.1  Install the High Speed Data Converter (HSDC) Pro Software
    2. 3.2  Install the Configuration GUI Software
    3. 3.3  Connect the EVM and TSW14J57EVM
    4. 3.4  Connect the Power Supplies to the Boards (Power Off)
    5. 3.5  Connect the Signal Generators to the EVM (RF Outputs Disabled Until Directed)
    6. 3.6  Turn On the TSW14J57EVM Power and Connect to the PC
    7. 3.7  Turn On the ADC12DJ5200RFEVM/SEEVM Power Supplies and Connect to the PC
    8. 3.8  Turn On the Signal Generator RF Outputs
    9. 3.9  Open the ADC12DJ5200RFEVM/SEEVM GUI and Program the ADC and Clocks
    10. 3.10 Calibrate the ADC Device on the EVM
    11. 3.11 Open the HSDC Software and Load the FPGA Image to the TSW14J57EVM
    12. 3.12 Capture Data Using the HSDC Pro Software
  5. 4Device Configuration
    1. 4.1 Supported JESD204C Device Features
    2. 4.2 Tab Organization
    3. 4.3 Low-Level Control
  6. 5Troubleshooting the ADC12DJ5200RFEVM/SEEVM
  7. 6References
    1. 6.1 Technical Reference Documents
    2. 6.2 TSW14J57EVM Operation
  8. 7HSDC Pro Settings for Optional ADC Device Configuration
    1. 7.1 Changing the Number of Frames per Multi-Frame (K)
    2. 7.2 Customizing the EVM for Optional Clocking Support
      1. 7.2.1 External Clocking Option (Default)
      2. 7.2.2 Onboard Clocking Option
      3. 7.2.3 External Reference Clocking Option
  9. 8Signal Routing
    1. 8.1 Signal Routing
  10.   A Analog Inputs
  11.   B Jumpers and LEDs
    1. 10.1 Jumper settings
  12.   B Revision History

3.5 Connect the Signal Generators to the EVM (RF Outputs Disabled Until Directed)

Connect a signal generator to the VIN input of the ADC12DJ5200RFEVM through a bandpass filter and attenuator at the SMA connector. This must be a low-noise signal generator. TI recommends a bandpass filter to filter the signal from the generator. Configure the signal generator for 2897 MHz, 6 dBm.

Note: ADC12DJ5200SE has an integrated input balun and extenal balun is not required. When using ADC12DJ5200SEEVM INAP(connector J5) should be used Channel A input and INBP(J6) should be used for channel B input. To appply an analog input signal use a bandpass filter to filter the signal from the generator. Configure the signal generator for 2897 MHz, 0 dBm.

When External Clocking is Used

  1. Connect a signal generator to the DEVCLK input of the EVM through a bandpass filter. This signal generator must be a low-noise signal generator. TI recommends a Trilithic-tunable bandpass filter to filter the signal coming from the generator. Configure the signal generator for the desired clock frequency in the range of 0.8 to 5.2 GHz. For best performance when using an RF signal generator, the power input to the CLK SMA connector must be 10 dBm (2.0 Vpp into 50 Ω). The signal generator must increase above 10 dBm by an amount equal to any additional attenuation in the clock signal path, such as the insertion loss of the bandpass filter. For example, if the filter insertion loss is 2 dB, the signal generator must be set to 10 dBm + 2 dB = 12 dBm.
  1. Connect a signal generator to the reference signal input of the EVM at REF CLK(J17). Configure the signal generator for the desired (260MHz) clock frequency. Set the output power to approximately 6–9 dBm.
    Note:
    1. The Reference clock frequency can be obtained from the ADC12DJ5200EVM GUI. Once the ADC12DJ5200EVM GUI is configured to the desired JMODE mode and clock rate. The Reference Clock frequency required by the EVM is displayed on first page of the GUI shown with red square in GUID-A2E0454D-9666-4AC7-B7A2-355927C7E4C8.html#SLAU7017106
    2. Ensure that the DEVCLK and Reference clock sources are frequency-locked using a common 10-MHz reference to ensure functionality. Frequency locking the input signal generator to the other generators can also be done if coherent sampling is desired.
    3. Do not turn on the RF output of any signal generator at this time.
    4. When using the ADC in single-input mode, the device uses both edges of DEVCLK for sampling.