SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
The timer has the capability to trigger the ADC when the TnOTE bit is set in the GPTMCTL register at offset 0x00C. The GPTM ADC Event (GPTMADCEV) register is additionally provided so that the type of ADC trigger can be defined. For example, by setting the CBMADCEN bit in the GPTMADCEV register, a trigger pulse will be sent to the ADC whenever a Capture Match event occurs in GPTM B. Similar to the µDMA operation, all active trigger events that have also been enabled in the GPTMADCEV register are ORed together to create an ADC trigger pulse.