| 31-20 |
RESERVED |
R |
0x0 |
|
| 19 |
DCINSS3 |
R |
0x0 |
Digital Comparator Interrupt Status on SS3.
This bit is cleared by writing a 1 to it.
Clearing this bit also clears the INRDC bit in the ADCRIS register.
0x0 = No interrupt has occurred or the interrupt is masked.
0x1 = Both the INRDC bit in the ADCRIS register and the DCONSS3 bit in the ADCIM register are set, providing a level-based interrupt to the interrupt controller.
|
| 18 |
DCINSS2 |
R |
0x0 |
Digital Comparator Interrupt Status on SS2.
This bit is cleared by writing a 1 to it.
Clearing this bit also clears the INRDC bit in the ADCRIS register.
0x0 = No interrupt has occurred or the interrupt is masked.
0x1 = Both the INRDC bit in the ADCRIS register and the DCONSS2 bit in the ADCIM register are set, providing a level-based interrupt to the interrupt controller.
|
| 17 |
DCINSS1 |
R |
0x0 |
Digital Comparator Interrupt Status on SS1.
This bit is cleared by writing a 1 to it.
Clearing this bit also clears the INRDC bit in the ADCRIS register.
0x0 = No interrupt has occurred or the interrupt is masked.
0x1 = Both the INRDC bit in the ADCRIS register and the DCONSS1 bit in the ADCIM register are set, providing a level-based interrupt to the interrupt controller.
|
| 16 |
DCINSS0 |
R |
0x0 |
Digital Comparator Interrupt Status on SS0.
This bit is cleared by writing a 1 to it.
Clearing this bit also clears the INRDC bit in the ADCRIS register.
0x0 = No interrupt has occurred or the interrupt is masked.
0x1 = Both the INRDC bit in the ADCRIS register and the DCONSS0 bit in the ADCIM register are set, providing a level-based interrupt to the interrupt controller.
|
| 15-12 |
RESERVED |
R |
0x0 |
|
| 11 |
DMAIN3 |
R/W1C |
0x0 |
SS3 DMA Interrupt Status and Clear.
This bit is cleared by writing a 1.
Clearing this bit also clears the DMAINR3 bit in the ADCRIS register.
0x0 = No interrupt has occurred or the interrupt is masked.
0x1 = Both the DMAINR3 bit in the ADCRIS register and the DMAMASK3 bit in the ADCIM register are set, providing a level-based interrupt to the interrupt controller.
|
| 10 |
DMAIN2 |
R/W1C |
0x0 |
SS2 DMA Interrupt Status and Clear.
This bit is cleared by writing a 1.
Clearing this bit also clears the DMAINR2 bit in the ADCRIS register.
0x0 = No interrupt has occurred or the interrupt is masked.
0x1 = Both the DMAINR2 bit in the ADCRIS register and the DMAMASK2 bit in the ADCIM register are set, providing a level-based interrupt to the interrupt controller.
|
| 9 |
DMAIN1 |
R/W1C |
0x0 |
SS1 DMA Interrupt Status and Clear.
This bit is cleared by writing a 1.
Clearing this bit also clears the DMAINR1 bit in the ADCRIS register.
0x0 = No interrupt has occurred or the interrupt is masked.
0x1 = Both the DMAINR1 bit in the ADCRIS register and the DMAMASK1 bit in the ADCIM register are set, providing a level-based interrupt to the interrupt controller.
|
| 8 |
DMAIN0 |
R/W1C |
0x0 |
SS0 DMA Interrupt Status and Clear.
This bit is cleared by writing a 1.
Clearing this bit also clears the DMAINR0 bit in the ADCRIS register.
0x0 = No interrupt has occurred or the interrupt is masked.
0x1 = Both the DMAINR0 bit in the ADCRIS register and the DMAMASK0 bit in the ADCIM register are set, providing a level-based interrupt to the interrupt controller.
|
| 7-4 |
RESERVED |
R |
0x0 |
|
| 3 |
IN3 |
R/W1C |
0x0 |
SS3 Interrupt Status and Clear.
This bit is cleared by writing a 1.
Clearing this bit also clears the INR3 bit in the ADCRIS register.
0x0 = No interrupt has occurred or the interrupt is masked.
0x1 = Both the INR3 bit in the ADCRIS register and the MASK3 bit in the ADCIM register are set, providing a level-based interrupt to the interrupt controller.
|
| 2 |
IN2 |
R/W1C |
0x0 |
SS2 Interrupt Status and Clear.
This bit is cleared by writing a 1.
Clearing this bit also clears the INR2 bit in the ADCRIS register.
0x0 = No interrupt has occurred or the interrupt is masked.
0x1 = Both the INR2 bit in the ADCRIS register and the MASK2 bit in the ADCIM register are set, providing a level-based interrupt to the interrupt controller.
|
| 1 |
IN1 |
R/W1C |
0x0 |
SS1 Interrupt Status and Clear.
This bit is cleared by writing a 1.
Clearing this bit also clears the INR1 bit in the ADCRIS register.
0x0 = No interrupt has occurred or the interrupt is masked.
0x1 = Both the INR1 bit in the ADCRIS register and the MASK1 bit in the ADCIM register are set, providing a level-based interrupt to the interrupt controller.
|
| 0 |
IN0 |
R/W1C |
0x0 |
SS0 Interrupt Status and Clear.
This bit is cleared by writing a 1.
Clearing this bit also clears the INR0 bit in the ADCRIS register.
0x0 = No interrupt has occurred or the interrupt is masked.
0x1 = Both the INR0 bit in the ADCRIS register and the MASK0 bit in the ADCIM register are set, providing a level-based interrupt to the interrupt controller.
|